NXP Semiconductors PXN2020 - 18.3.2.3 MPU Error Detail Register, MPU Port 0 to 3 (MPU_EDRn)

Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 18-7
18.3.2.3 MPU Error Detail Register, MPU Port 0 to 3 (MPU_EDRn)
When the MPU detects an access error on MPU port n, 32 bits of error detail are captured in this read-only
register and the corresponding bit in the MPU_CESR[MPERR] field set. Information on the faulting
address is captured in the corresponding MPU_EARn register at the same time.
Offset: MPU_BASE + 0x0010 (MPU_EAR0)
MPU_BASE + 0x0018 (MPU_EAR1)
MPU_BASE + 0x0020 (MPU_EAR2)
MPU_BASE + 0x0028 (MPU_EAR3)
Access: User read-only
0123456789101112131415
R EADDR
W
Reset––––––––––––––––
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EADDR
W
Reset––––––––––––––––
Figure 18-4. MPU Error Address Register, MPU Port n (MPU_EARn)
Table 18-4. MPU_EARn Field Descriptions
Field Description
EADDR Error Address. This read-only field is the reference address from MPU port n that generated the access error.
Offset: MPU_BASE + 0x00014 (MPU_EDR0)
MPU_BASE + 0x001C (MPU_EDR1)
MPU_BASE + 0x0024 (MPU_EDR2)
MPU_BASE + 0x002C (MPU_EDR3)
Access: User read-only
0123456789101112131415
R EACD
W
Reset–––––––––––––– ––
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EPID EMN EATTR ERW
W
Reset–––––––––––––– ––
Figure 18-5. MPU Error Detail Register, MPU Port 0 to 3 (MPU_EDRn)