Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 1-9
1.7.4 On-Chip SRAM
On-chip SRAM on the PXN20 family features the following:
• Up to 592/128 KB general purpose RAM
• Two RAM blocks implemented on separate crossbar ports to reduce arbitration events for high
access master to on-chip RAM.
— One port with 80 KB (PXN20 only)
— One port with 512/128 KB RAM
• Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit
writes if back to back with a read to same memory block
• 32-bit ECC with single-bit correction, double bit detection for data integrity
• Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
• User transparent ECC encoding and decoding for byte, half word, and word accesses
1.7.5 On-Chip Voltage Regulator (VREG)
The on-chip voltage regulator includes the following features:
• Single supply device
• 3.3 V / 5 V (nominal) input supply voltage supported
• Supports I/O levels independent of main supply
— MLB has separate supply pins to support down to 2.5 V (nominal) operation
— Multiple I/O domains with separate supply pins
• Low voltage detectors (LVD) supported on internal supplies
• Cold crank operation supported without triggering LVDs
1.7.6 Fast Ethernet Controller (FEC)
The FEC incorporates the following features
• Support for 3 different physical interfaces
— 100 Mbps IEEE 802.3 MII
— 10 Mbps IEEE 802.3 MII
— 10 Mbps 7-wire interface (industry standard)
• Built in FIFO and DMA controller
• IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition)
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• IEEE 802.3 full duplex flow control
• Support for full duplex operation (200 Mbps throughput) with a system clock of 100 MHz using
the external TX_CLK or RX_CLK
• Support for full duplex operation(100 Mbps throughput) with a system clock of 50 MHz using the
external TX_CLK or RX_CLK
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