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NXP Semiconductors PXN2020 - Chapter 32 Inter-Integrated Circuit Bus Controller Module (I2 C); 32.1 Introduction; 32.1.1 Block Diagram

NXP Semiconductors PXN2020
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 32-1
Chapter 32
Inter-Integrated Circuit Bus Controller Module (I
2
C)
32.1 Introduction
The inter-integrated circuit (I
2
C™) bus is a two-wire bidirectional serial bus that provides a simple and
efficient method of data exchange between devices. It minimizes the external connections to devices and
does not require an external address decoder.
This bus is suitable for applications requiring occasional communication over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate as fast as 100 kbps with maximum bus loading and timing. The device
is capable of operating at higher baud rates, as fast as a maximum of module clock/20, with reduced bus
loading. The maximum communication length and the number of devices that can be connected are limited
by a maximum bus capacitance of 400 pF.
The PXN20 provides four functionally identical I
2
C modules, identified as I
2
C_A through I
2
C_D.
32.1.1 Block Diagram
A simplified block diagram of the I
2
C illustrates the functionality and interdependence of major blocks
(see Figure 32-1).

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