NXP Semiconductors PXN2020 - 26.6.11 External Clock Synchronization

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-134 Freescale Semiconductor
Figure 26-140. Single Channel Device Mode (Channel A)
Figure 26-141. Single Channel Device Mode (Channel B)
26.6.11 External Clock Synchronization
The application of the external rate and offset correction is triggered when the application writes to the
EOC_AP and ERC_AP fields in the Protocol Operation Control Register (POCR). The PE applies the
external correction values in the next even-odd cycle pair as shown in Figure 26-142 and Figure 26-143.
CHI
PE
cfg(A)
reg(A)
cCrcInit[A]
cCrcInit[B]
cfg(B)
reg(B)
channel A
channel B
FlexRay Channel A
FlexRay Bus Driver
Channel A
FR_A_RX
FR_A_TX
FR_A_TX_EN
FR_B_RX
FR_B_TX
FR_B_TX_EN
FlexRay
CHI
PE
cfg(A)
reg(A)
cCrcInit[B]
cfg(B)
reg(B)
channel A
channel B
FlexRay Channel B
Init Value for Frame CRC is cCrcInit[B]
cCrcInit[A]
FlexRay Bus Driver
Channel A
FR_A_RX
FR_A_TX
FR_A_TX_EN
FR_B_RX
FR_B_TX
FR_B_TX_EN
FlexRay