NXP Semiconductors PXN2020 - 29.1.2 Features

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Controller Area Network (FlexCAN)

PXN20 Microcontroller Reference Manual, Rev. 1

29-2 Freescale Semiconductor

Figure 29-1. FlexCAN Block Diagram

29.1.2 Features

The FlexCAN has these major features:

• Full implementation of the CAN protocol specification, Version 2.0A/B

— Standard data and remote frames

— Extended data and remote frames

— Zero to eight bytes data length

— Programmable bit rate as high as 1 Mbit/s

— Content-related addressing

• 64 flexible message buffers (MBs) of 0 to 8 bytes data length

• Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

MB3

RAM

Bus Interface Unit

max MB #

(0–63)

Slave Interface

CAN

Message

CNTXx

CNRXx

MB2

MB1

MB0

MB60

MB61

MB62

MB63

Clocks, Address and Data Buses,

Interrupt and Test Signals

Buffer

Management

Protocol

Interface

1 KB

RXIMR63

RXIMR62

RXIMR1

RXIMR0

ID Mask

Storage

256 bytes

RAM

FlexCAN

Main Page

PXN20 Microcontroller Reference Manual1
About This Book33
Suggested Reading35
Chapter 1 Introduction43
- 1.1 Overview43
- 1.2 PXN20 Features43
- 1.3 PXN20 Block Diagram45
- 1.4 PXN21 Block Diagram46
- 1.5 Critical Performance Parameters47
  - 1.5.1 Low Power Operation47
- 1.6 Packages48
- 1.7 Module Features48
- 1.8 Developer Support63
Chapter 2 Memory Map65
- 2.1 Introduction65
Chapter 3 Signal Description69
- 3.1 Introduction69
- 3.2 Signal Properties Summary69
  - 3.2.1 I/O Power and Ground Segmentation86
- 3.3 Pinout87
- 3.4 Detailed Signal Description89
Chapter 4 Resets113
- 4.1 Introduction113
- 4.2 External Signal Description113
  - 4.2.1 Reset (RESET)114
  - 4.2.2 Boot Configuration (BOOTCFG)114
- 4.3 Functional Description114
  - 4.3.1 Z6, Z0 Cores Reset Vectors114
  - 4.3.2 Reset Sources114
- 4.4 Reset Configuration116
  - 4.4.1 Reset Configuration Timing117
Chapter 5 System Clock Description119
- 5.1 Introduction119
- 5.2 System Clock Architecture124
- 5.3 Clock Dividers126
- 5.4 Software-Controlled Power Management128
- 5.5 Alternate Module Clock Domains130
Chapter 6 Clocks, Reset, and Power (CRP)133
- 6.1 Introduction133
- 6.2 Memory Map and Registers136
  - 6.2.1 Module Memory Map136
  - 6.2.2 Register Descriptions137
- 6.3 Functional Description149
- 6.4 Real-Time Counter (RTC)157
- 6.5 Power Supply Monitors161
  - 6.5.1 Power-On Reset (POR)161
  - 6.5.2 Low-Voltage Monitors (LVI)161
Chapter 7 Frequency Modulated Phase-Locked Loop (FMPLL)163
- 7.1 Introduction163
- 7.2 External Signal Description164
- 7.3 Memory Map and Registers164
  - 7.3.1 Module Memory Map164
  - 7.3.2 Register Descriptions165
- 7.4 Functional Description172
- 7.5 Resets180
- 7.6 Interrupts181
  - 7.6.1 Loss-of-Lock Interrupt Request181
  - 7.6.2 Loss-of-Clock Interrupt Request181
Chapter 8 System Integration Unit (SIU)183
- 8.1 Introduction183
- 8.2 External Signal Description185
  - 8.2.1 Ports vs. General-Purpose I/O Pins186
- 8.3 Memory Map and Registers186
  - 8.3.1 Module Memory Map186
  - 8.3.2 Register Descriptions195
- 8.4 Functional Description250
Chapter 9 Boot Assist Module (BAM)255
- 9.1 Introduction255
  - 9.1.1 Features255
  - 9.1.2 Modes of Operation256
- 9.2 Memory Map and Registers256
  - 9.2.1 Module Memory Map256
  - 9.2.2 Register Descriptions257
- 9.3 Functional Description257
Chapter 10 Interrupts and Interrupt Controller (INTC)269
- 10.1 Introduction269
- 10.2 External Signal Description275
- 10.3 Memory Map and Registers276
  - 10.3.1 INTC Memory Map276
  - 10.3.2 Register Descriptions277
- 10.4 Functional Description287
- 10.5 Initialization/Application Information306
- 10.6 Non-Maskable Interrupt (NMI)315
- 10.7 Dynamic Interrupt Priority Elevation316
Chapter 11 General-Purpose Static RAM (SRAM)319
- 11.1 Introduction319
- 11.2 External Signal Description321
- 11.3 Memory Map and Registers321
- 11.4 Functional Description321
- 11.5 SRAM ECC Mechanism321
  - 11.5.1 Access Timing322
  - 11.5.2 Reset Operation323
- 11.6 DMA Requests324
- 11.7 Interrupt Requests324
- 11.8 Initialization and Application Information324
  - 11.8.1 Example Code324
Chapter 12 Flash Memory Array and Control327
- 12.1 Introduction327
- 12.2 External Signal Description330
- 12.3 Memory Map and Registers330
  - 12.3.1 Module Memory Map330
  - 12.3.2 Register Descriptions332
- 12.4 Functional Description353
Chapter 13 e200z6 Core (Z6)365
- 13.1 Introduction365
- 13.2 Core Registers and Programmer’s Model370
- 13.3 Functional Description378
- 13.4 Power Architecture Instruction Extensions - VLE397
- 13.5 External References398
Chapter 14 e200z0 Core (Z0)399
- 14.1 Introduction399
  - 14.1.1 Features399
- 14.2 Microarchitecture Summary400
- 14.3 Core Registers and Programmer’s Model403
- 14.4 Interrupt Types409
- 14.5 Bus Interface Unit (BIU)411
Chapter 15 Semaphores413
- 15.1 Introduction413
- 15.2 Signal Description415
- 15.3 Memory Map and Registers415
  - 15.3.1 Module Memory Map415
  - 15.3.2 Register Descriptions416
- 15.4 Functional Description422
  - 15.4.1 Semaphore Usage424
- 15.5 Initialization Information424
- 15.6 Application Information424
- 15.7 DMA Requests426
- 15.8 Interrupt Requests426
Chapter 16 AMBA Crossbar Switch (AXBS)427
- 16.1 Introduction427
- 16.2 Memory Map and Register Definition429
  - 16.2.1 Register Descriptions430
- 16.3 Functional Description434
Chapter 17 Peripheral Bridge (AIPS-lite)439
- 17.1 Introduction439
- 17.2 External Signal Description440
- 17.3 Memory Map and Register Description440
- 17.4 Functional Description440
  - 17.4.1 Read Cycles440
  - 17.4.2 Write Cycles440
Chapter 18 Memory Protection Unit (MPU)441
- 18.1 Introduction441
- 18.2 Signal Description443
- 18.3 Memory Map and Registers443
  - 18.3.1 Module Memory Map443
  - 18.3.2 Register Descriptions445
- 18.4 Functional Description455
  - 18.4.1 Access Evaluation Macro455
    - 18.4.1.1 Access Evaluation-Hit Determination456
    - 18.4.1.2 Access Evaluation-Privilege Violation Determination456
  - 18.4.2 Putting It All Together and AHB Error Terminations457
- 18.5 Initialization Information457
- 18.6 Application Information458
Chapter 19 Error Correction Status Module (ECSM)461
- 19.1 Introduction461
  - 19.1.1 Features461
- 19.2 Memory Map and Registers461
  - 19.2.1 Module Memory Map462
  - 19.2.2 Register Descriptions463
Chapter 20 Software Watchdog Timer (SWT)479
- 20.1 Introduction479
  - 20.1.1 Features479
  - 20.1.2 Modes of Operation479
- 20.2 External Signal Description479
- 20.3 Memory Map and Register Definition480
  - 20.3.1 Memory Map480
  - 20.3.2 Register Descriptions480
- 20.4 Functional Description485
Chapter 21 System Timer Module (STM)489
- 21.1 Overview489
- 21.2 External Signal Description489
- 21.3 Memory Map and Register Definition490
  - 21.3.1 Memory Map490
  - 21.3.2 Register Descriptions490
- 21.4 Functional Description493
Chapter 22 Periodic Interrupt Timer (PIT)495
- 22.1 Introduction495
- 22.2 Signal Description496
  - 22.2.1 External Signal Description496
- 22.3 Memory Map and Registers496
  - 22.3.1 Module Memory Map496
  - 22.3.2 Register Descriptions498
- 22.4 Functional Description502
- 22.5 Initialization and Application Information503
  - 22.5.1 Example Configuration503
Chapter 23 DMA Channel Multiplexer (DMA_MUX)505
- 23.1 Introduction505
- 23.2 External Signal Description506
- 23.3 Memory Map and Registers506
  - 23.3.1 Module Memory Map506
  - 23.3.2 Register Descriptions508
    - 23.3.2.1 Channel Configuration Registers (CHCONFIGx)508
- 23.4 Functional Description512
- 23.5 Initialization/Application Information516
  - 23.5.1 Reset516
  - 23.5.2 Enabling and Configuring Sources516
- 23.6 Interrupts520
Chapter 24 Enhanced Direct Memory Access Controller (eDMA)521
- 24.1 Introduction521
- 24.2 External Signal Description523
- 24.3 Memory Map and Registers523
  - 24.3.1 Module Memory Map523
  - 24.3.2 Register Descriptions527
- 24.4 Functional Description549
  - 24.4.1 eDMA Basic Data Flow551
- 24.5 Initialization / Application Information554
Chapter 25 Fast Ethernet Controller (FEC)567
- 25.1 Introduction567
- 25.2 Modes of Operation570
- 25.3 Programming Model571
- 25.4 Functional Description595
- 25.5 Buffer Descriptors609
Chapter 26 FlexRay Communication Controller (FlexRAY)615
- 26.1 Introduction615
- 26.2 External Signal Description620
  - 26.2.1 Detailed Signal Descriptions620
- 26.3 Controller Host Interface Clocking621
- 26.4 Protocol Engine Clocking622
  - 26.4.1 Oscillator Clocking622
  - 26.4.2 PLL Clocking622
- 26.5 Memory Map and Register Description622
  - 26.5.1 Memory Map622
  - 26.5.2 Register Descriptions625
- 26.6 Functional Description692
- 26.7 Application Information766
Chapter 27 Media Local Bus (MLB)773
- 27.1 Introduction773
- 27.2 External Signal Description775
- 27.3 Memory Map and Register Description776
  - 27.3.1 Memory Map776
  - 27.3.2 Register Descriptions780
- 27.4 Functional Description798
- 27.5 Initialization Information811
Chapter 28 Enhanced Modular Input/Output Subsystem (eMIOS200)823
- 28.1 Introduction823
- 28.2 External Signal Description828
  - 28.2.1 eMIOS[n]828
  - 28.2.2 Output Disable Input - eMIOS200 Output Disable Input Signal828
- 28.3 Memory Map and Register Description828
  - 28.3.1 Memory Map828
  - 28.3.2 Register Descriptions830
- 28.4 Functional Description842
- 28.5 Reset881
- 28.6 Interrupts881
- 28.7 DMA Requests881
- 28.8 Initialization/Application Information882
Chapter 29 Controller Area Network (FlexCAN)885
- 29.1 Introduction885
- 29.2 External Signal Description888
- 29.3 Memory Map and Registers888
- 29.4 Functional Description911
- 29.5 Initialization and Application Information924
  - 29.5.1 FlexCAN Initialization Sequence924
Chapter 30 Deserial - Serial Peripheral Interface (DSPI)927
- 30.1 Introduction927
- 30.2 External Signal Description931
- 30.3 Memory Map and Registers931
  - 30.3.1 Module Memory Map931
  - 30.3.2 Register Descriptions933
- 30.4 Functional Description954
- 30.5 Initialization/Application Information985
Chapter 31 Enhanced Serial Communication Interface (eSCI)991
- 31.1 Introduction991
- 31.2 External Signal Description994
- 31.3 Memory Map and Registers994
  - 31.3.1 Memory Map994
  - 31.3.2 Register Descriptions995
- 31.4 Functional Description1010
- 31.5 Application Information1042
  - 31.5.1 SCI Data Frames Separated by Preamble1042
Chapter 32 Inter-Integrated Circuit Bus Controller Module (I2C)1045
- 32.1 Introduction1045
- 32.2 External Signal Description1048
- 32.3 Memory Map and Registers1048
  - 32.3.1 Module Memory Map1048
  - 32.3.2 Register Descriptions1049
- 32.4 Functional Description1055
  - 32.4.1 I-Bus Protocol1055
  - 32.4.2 Interrupts1059
    - 32.4.2.1 General1059
    - 32.4.2.2 Interrupt Description1059
- 32.5 Initialization/Application Information1060
  - 32.5.1 I2C Programming Examples1060
  - 32.5.2 DMA Application Information1064
Chapter 33 Cross Triggering Unit (CTU)1069
- 33.1 Introduction1069
- 33.2 Main Features1069
- 33.3 Block Diagram1069
- 33.4 Memory Map and Register Description1070
  - 33.4.1 Module Memory Map1070
- 33.5 Functional Description1075
Chapter 34 Analog-to-Digital Converter (ADC)1081
- 34.1 Introduction1081
  - 34.1.1 Block Diagram1081
  - 34.1.2 Features1082
- 34.2 External Signals1082
- 34.3 Memory Map and Register Definition1083
  - 34.3.1 ADC Memory Map1083
  - 34.3.2 ADC Register Descriptions1088
- 34.4 Functional Description1121
Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC)1135
- 35.1 Introduction1135
- 35.2 External Signal Description1139
- 35.3 Memory Map and Registers1139
- 35.4 Functional Description1140
- 35.5 e200z0 and e200z6 OnCE Controllers1146
- 35.6 Initialization/Application Information1149
Chapter 36 Nexus Development Interface (NDI)1151
- 36.1 Introduction1151
- 36.2 Block Diagram1151
  - 36.2.1 NDI Features1153
  - 36.2.2 Modes of Operation1155
- 36.3 External Signal Description1156
- 36.4 Memory Map and Registers1157
  - 36.4.1 NDI Functional Description1159
- 36.5 Nexus Port Controller (NPC)1163
- 36.6 e200z6 Class 3 Nexus Module (Nexus3+)1174
- 36.7 e200z0 Class 2+ Nexus Module (Nexus2+)1220
- 36.8 Debug Implementation1252
- 36.9 Debug Capabilities1252
- 36.10 Debug Port1254
  - 36.10.1 Nexus2+/3 Auxiliary Port1255
- 36.11 Debug Methods1256
  - 36.11.1 208 MAPBGA Package Debug Method1256
  - 36.11.2 256 MAPBGA Package Debug Method1256
Appendix A Memory Map1259

NXP Semiconductors PXN2020 - 29.1.2 Features

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