NXP Semiconductors PXN2020 - 24.3.2.15 DMA Hardware Request Status (EDMA

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Enhanced Direct Memory Access Controller (eDMA)

PXN20 Microcontroller Reference Manual, Rev. 1

Freescale Semiconductor 24-21

The contents of this register can also be polled and a non-zero value indicates the presence of a channel

error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in

this register and it provides a single bit indication of any errors. The state of any given channel’s error

indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes

to EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit

position has no effect on the corresponding channel’s current error status. The EDMA_CER is provided

so the error indicator for a single channel can be cleared.

24.3.2.15 DMA Hardware Request Status (EDMA_HRSL)

The EDMA_HRSL registers provide a bit map for the implemented channels (32) to show the current

hardware request status for each channel. EDMA_HRSL covers channels 31–00.

See Table 24-17 for the EDMA_HRSL definition.

Offset: EDMA_BASE + 0x002C Access: User read-only

0123456789101112131415

RERR

ERR

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RERR

ERR

Reset0000000000000000

Figure 24-15. eDMA Error Register (EDMA_ERL)

Table 24-16. EDMA_ERL Field Descriptions

Field Description

ERRn eDMA Error n.

0 An error in channel n has not occurred.

1 An error in channel n has occurred.

NXP Semiconductors PXN2020 - 24.3.2.15 DMA Hardware Request Status (EDMA_HRSL)