Error Correction Status Module (ECSM)
PXN20 Microcontroller Reference Manual, Rev. 1
19-16 Freescale Semiconductor
19.2.2.13 Platform RAM ECC Data Register (PREDR)
The PREDR is a 64-bit register for capturing the data associated with the last properly enabled ECC event
in the platform RAM memory. Depending on the state of the ECC configuration register, an ECC event in
the platform RAM causes the address, attributes, and data associated with the access to be loaded into the
PREAR, PRESR, PREMR, PREAT, and PREDR registers and also the appropriate flag (PR1BC or
PRNCE) in the ECC status register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined. This register is read-only; any
attempted write is ignored. See Figure 19-15 and Table 19-16 for the platform RAM ECC data register
definition.
SIZE 000 8-bit access.
001 16-bit access.
010 32-bit access.
011 64-bit access.
1xx Reserved.
PROTEC
TION
Cache:
0xxx Non-cacheable.
1xxx Cacheable.
Buffer:
x0xx Non-bufferable.
x1xx Bufferable.
Mode:
xx0x User mode.
xx1x Supervisor mode.
Typ e:
xxx0 I-Fetch.
xxx1 Data.
Offset: ECSM_BASE_ADDR + 0x0068 Access: User read-only
0 123456789101112131415
R PREDR[0:15]
W
ResetU UUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PREDR[16:31]
W
ResetU UUUUUUUUUUUUUUU
Figure 19-14. Platform RAM ECC Data High (PREDRH) Register
Table 19-15. PREAT Field Descriptions (continued)
Field Description
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