NXP Semiconductors PXN2020 - 26.5.2.34 Sync Frame ID Rejection Filter Register (SFIDRFR)

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-44 Freescale Semiconductor
26.5.2.34 Sync Frame ID Rejection Filter Register (SFIDRFR)
This register defines the Sync Frame Rejection Filter ID. The application must update this register outside
of the static segment. If the application updates this register in the static segment, it can appear that the
controller accepts the sync frame in the current cycle.
OPT One Pair Trigger — This trigger bit controls whether the controller writes continuously or only one pair of
Sync Frame Tables into the FlexRay memory.
If this trigger is set to 1 while SDVEN or SIDEN is set to 1, the controller writes only one pair of the enabled
Sync Frame Tables corresponding to the next even-odd-cycle pair into the FlexRay memory. In this case, the
controller clears the SDVEN or SIDEN bits immediately.
If this trigger is set to 0 while SDVEN or SIDEN is set to 1, the controller writes continuously the enabled Sync
Frame Tables into the FlexRay memory.
0 Write continuously pairs of enabled Sync Frame Tables into FlexRay memory.
1 Write only one pair of enabled Sync Frame Tables into FlexRay memory.
SDVEN Sync Frame Deviation Table Enable — This bit controls the generation of the Sync Frame Deviation Tables.
The application must set this bit to request the controller to write the Sync Frame Deviation Tables into the
FlexRay memory.
0 Do not write Sync Frame Deviation Tables.
1 Write Sync Frame Deviation Tables into FlexRay memory.
Note: If SDVEN is set to 1, then SIDEN must also be set to 1.
SIDEN Sync Frame ID Table Enable — This bit controls the generation of the Sync Frame ID Tables. The
application must set this bit to 1 to request the controller to write the Sync Frame ID Tables into the FlexRay
memory.
0 Do not write Sync Frame ID Tables.
1 Write Sync Frame ID Tables into FlexRay memory.
Base + 0x0046 16-bit write access required Write: Normal Mode
0123456789101112131415
R000000
SYNFRID
W
Reset0000000000000000
Figure 26-34. Sync Frame ID Rejection Filter Register (SFIDRFR)
Table 26-40. SFIDRFR Field Descriptions
Field Description
SYNFRID Sync Frame Rejection ID — This field defines the frame ID of a frame that must not be used for clock
synchronization. For details see Section 26.6.15.2, Sync Frame Rejection Filtering.
Table 26-39. SFTCCSR Field Descriptions (continued)
Field Description