NXP Semiconductors PXN2020 - 7.1.3 Modes of Operation; 7.2 External Signal Description; 7.3 Memory Map and Registers; 7.3.1 Module Memory Map

Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
7-2 Freescale Semiconductor
• Because the PXN20 uses a 16 MHz IRC as its default system clock, the FMPLL is put in PLL Off
mode during reset, so that power dissipation is minimized by disabling the FMPLL until needed
by the system.
• Programmable frequency multiplication factor settings generating VCO frequencies of
192 MHz – 600 MHz
• PLL Off mode (low-power mode)
• Register programmable output clock divider (ERFD)
• Programmable frequency modulation
— Modulation applied as a triangle waveform
— Peak-to-peak register programmable modulation depths of 0.5%, 1%, 1.5%, and 2% of the
system frequency
— Register programmable modulation rates of F
extal
/80, F
extal
/40, and F
extal
/20
• Lock detect circuitry provides a signal indicating the FMPLL has acquired lock and continuously
monitors the FMPLL output for any loss of lock
• Loss-of-clock circuitry monitors input reference and FMPLL output clocks with programmable
ability to select a backup clock source as well as generate a reset or interrupt in the event of a failure
7.1.3 Modes of Operation
There are two main modes of FMPLL: PLL Off mode and normal mode. These modes are briefly
described in this section.
When PLL Off mode is selected, the FMPLL is turned off and the end-system user must select a different
source than the PLL output in SIU_SYSCLK[SYSCLKSEL]. The lock detector is not functional and does
not indicate that the FMPLL is in a locked state. Frequency modulation is not available and the FMPLL is
put into a low-power, idle state. This operating mode is described in Section 7.4.2, PLL Off Mode.
When normal mode is selected, the FMPLL is fully programmable. The FMPLL reference clock source
can be a crystal oscillator or an external clock generator. The lock detector indicates the lock status of the
FMPLL, and frequency modulation of the output clock can be enabled. This operating mode is described
in Section 7.4.3, Normal Mode.
7.2 External Signal Description
Refer to Table 3-1 and Section 3.4, Detailed Signal Description, for detailed signal descriptions.
7.3 Memory Map and Registers
This section provides a detailed description of the FMPLL registers.
7.3.1 Module Memory Map
Table 7-1 shows the FMPLL memory map. The address of each register is given as an offset to the FMPLL
base address. Registers are listed in address order, identified by complete name and mnemonic, and lists
the type of accesses allowed.