Error Correction Status Module (ECSM)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 19-13
19.2.2.10 Platform RAM ECC Syndrome Register (PRESR)
The PRESR is an 8-bit register for capturing the error syndrome of the last properly enabled ECC event in
the platform RAM memory. Depending on the state of the ECC configuration register, an ECC event in
the platform RAM causes the address, attributes, and data associated with the access to be loaded into the
PREAR, PRESR, PREMR, PREAT and PREDR registers, and the appropriate flag (PR1BC or PRNCE)
in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 19-11 and Table 19-12 for the
Platform RAM ECC syndrome register definition.
Offset: ECSM_BASE_ADDR + 0x0060 Access: User read-only
0 123456789101112131415
R PREAR
W
ResetU UUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PREAR
W
ResetU UUUUUUUUUUUUUUU
Figure 19-10. Platform RAM ECC Address (PREAR) Register
Table 19-11. PREAR Field Descriptions
Field Description
PREAR Platform RAM ECC Address Register. Contains the faulting access address of the last properly enabled platform
RAM ECC event.
Offset: ECSM_BASE_ADDR + 0x0065 Access: User read-only
01234567
R PRESR[0:7]
W
ResetUUUUUUUU
Figure 19-11. Platform RAM ECC Syndrome (PRESR) Register
Table 19-12. PRESR Field Descriptions
Field Description
PRESR Platform RAM ECC Syndrome Register. This 8-bit syndrome field includes 7 bits of Hamming decoded parity plus
an odd-parity bit for the entire 72-bit (64-bit data + 8 ECC) code word. The upper 7 bits of the syndrome specify the
exact bit position in error for single-bit correctable codewords, and the combination of a non-zero 7-bit syndrome
plus overall incorrect parity bit signal a multi-bit, non-correctable error.
For correctable single-bit errors, the mapping shown in Table 19-13 associates the upper 7 bits of the syndrome
with the data bit in error.
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