FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-55
NOTE
If the counter has reached its maximum value 0xFFFF and is in the
multicycle mode (SSCCRn[MCY] = 1), the counter is not reset to 0x0000.
The application can reset the counter by clearing the SSCCRn[MCY] bit
and waiting for the next cycle start, when the controller clears the counter.
Subsequently, the counter can be set into the multicycle mode again.
26.5.2.48 MTS A Configuration Register (MTSACFR)
This register controls the transmission of the Media Access Test Symbol MTS on channel A. For more
details, see Section 26.6.13, MTS Generation.
26.5.2.49 MTS B Configuration Register (MTSBCFR)
This register controls the transmission of the Media Access Test Symbol MTS on channel B. For more
details, see Section 26.6.13, MTS Generation.
Table 26-56. SSCR0–SSCR3 Field Descriptions
Field Description
SLOTSTATUSCNT Slot Status Counter — This field provides the current value of the Slot Status Counter.
Base + 0x0080 Write: MTE: Anytime
CYCCNTMSK,CYCCNTVAL:POC:config
0123456789101112131415
R
MTE
0
CYCCNTMSK
00
CYCCNTVAL
W
Reset0000000000000000
Figure 26-48. MTS A Configuration Register (MTSACFR)
Table 26-57. MTSACFR Field Descriptions
Field Description
MTE Media Access Test Symbol Transmission Enable — This control bit is used to enable and disable the
transmission of the Media Access Test Symbol in the selected set of cycles.
0 MTS transmission disabled.
1 MTS transmission enabled.
CYCCNTMSK Cycle Counter Mask — This field provides the filter mask for the MTS cycle count filter.
CYCCNTVAL Cycle Counter Value — This field provides the filter value for the MTS cycle count filter.
Base + 0x0082 Write: MTE: Anytime
CYCCNTMSK,CYCCNTVAL:POC:config
0123456789101112131415
R
MTE
0
CYCCNTMSK
00
CYCCNTVAL
W
Reset0000000000000000
Figure 26-49. MTS B Configuration Register (MTSBCFR)
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