NXP Semiconductors PXN2020 - 8.3.2.42 Masked Parallel GPIO Pin Data Output Register 6 (SIU_MPGPDO6); 8.3.2.43 Masked Parallel GPIO Pin Data Output Register 7 (SIU_MPGPDO7)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-55
8.3.2.42 Masked Parallel GPIO Pin Data Output Register 6 (SIU_MPGPDO6)
The SIU_MPGPDO6 register contains the masked parallel GPIO pin data output for PG[0:15]
Writes to this register are coherent with registers SIU_GPDO96_99, SIU_GPDO100_103,
SIU_GPDO104_107, and SIU_GPDO108_111.
8.3.2.43 Masked Parallel GPIO Pin Data Output Register 7 (SIU_MPGPDO7)
The SIU_MPGPDO7 register contains the masked parallel GPIO pin data output for PH[0:15].
Writes to this register are coherent with registers SIU_GPDO112_115, SIU_GPDO116_119,
SIU_GPDO120_123, and SIU_GPDO124_127.
Offset: SIU_BASE + 0x0C94 Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PF_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PF[0:15]
Reset0000000000000000
Figure 8-49. Masked Parallel GPIO Pin Data Output Register 5 (SIU_MPGPDO5)
Offset: SIU_BASE + 0x0C98 Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PG_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PG[0:15]
Reset0000000000000000
Figure 8-50. Masked Parallel GPIO Pin Data Output Register 6 (SIU_MPGPDO6)