NXP Semiconductors PXN2020 - 28.3.2.2 eMIOS200 Global Flag Register (EMIOS_GFR)

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-10 Freescale Semiconductor
28.3.2.2 eMIOS200 Global Flag Register (EMIOS_GFR)
GPREN Global Prescaler Enable Bit. The GPREN bit enables the prescaler counter.
0 Prescaler disabled (no clock) and prescaler counter is cleared.
1 Prescaler enabled.
GPRE Global Prescaler Bits. The GPRE bits select the clock divider value for the global prescaler.
Offset: EMIOS_BASE + 0x0004 Access: User read-only
0123456789101112131415
RF31F30F29F28F27F26F25F24F23F22F21F20F19F18F17F16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RF15F14F13F12F11F10F9F8F7F6F5F4F3F2F1F0
W
Reset0000000000000000
Figure 28-4. eMIOS200 Global Flag Register (EMIOS_GFR)
Table 28-6. EMIOS_GFR Field Descriptions
Field Description
F[31:0] FLAG Bits 23–0. The EMIOS_GFR is a read-only register that groups the FLAG bits from all channels. This
organization improves interrupt handling on simpler devices. These bits are mirrors of the FLAG bits of each
channel register (EMIOS_CSRn).
The PXN21 implements all 32 channels, comprising bits F31 through F0. The PXN20 implements only 24
channels, comprising bits F23 through F0.
Table 28-5. EMIOS_MCR Field Descriptions (continued)
Field Description
GPRE Divide Ratio
0000_0000 1
0000_0001 2
0000_0010 3
0000_0011 4
.
.
.
.
.
.
1111_1110 255
1111_1111 256