NXP Semiconductors PXN2020 - 18.1.3 Modes of Operation; 18.2 Signal Description; 18.3 Memory Map and Registers; 18.3.1 Module Memory Map

Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 18-3
— Two types of access control definitions: two processor core bus masters (e200z6 and e200z0)
support the traditional {read, write, execute} permissions with independent definitions for
supervisor and user mode accesses; the remaining three non-core bus masters (DMA, FlexRay,
and AIPS) support {read, write} attributes
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated
with maintaining a coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient
mechanism to dynamically alter the access rights of a descriptor only
— For overlapping region descriptors, priority is given to permission granting over access
denying as this approach provides more flexibility to system software
• Support for four AHB MPU port connections
— AIPS_A, AIPS_B, SRAM_A, SRAM_B
— MPU hardware monitors every AHB MPU port access using the pre-programmed memory
region descriptors
— An access protection error is detected if a memory reference does not hit in any memory region
or the reference is flagged as illegal in all memory regions where it does hit; in the event of an
access error, the AHB reference is terminated with an error response and the MPU inhibits the
bus cycle being sent to the targeted slave device
— 64-bit error registers, one for each AHB MPU port, capture the last faulting address, attributes,
and detail information
18.1.3 Modes of Operation
The MPU does not support any special modes of operation.
18.2 Signal Description
The MPU does not include any external signals.
18.3 Memory Map and Registers
This section provides a detailed description of all MPU registers.
18.3.1 Module Memory Map
The MPU memory map is shown in Table 18-2. The address of each register is given as an offset to the
MPU base address. Registers are listed in address order, identified by complete name and mnemonic, and
list the type of accesses allowed.
The MPU registers can be referenced using 32-bit (word) accesses only. Attempted references using
different access sizes, to undefined (reserved) addresses, or with a non-supported access type (for example,
a write to a read-only register or a read of a write-only register) generate an error termination.