Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-32 Freescale Semiconductor
flag TC in the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set and the internal commit bit
iCMT is cleared.
31.4.5.3 Receiver
The receiver supports the reception of all data frame types defined in Table 31-15 and Table 31-16, of all
break characters defined in Table 31-17, and of all idle characters defined in Table 31-18.
31.4.5.3.1 Receiver States and Transitions
The receiver has four basic states that are shown and described in Table 31-26. The state transitions that
can triggered by the application commands are shown in Table 31-27. The state transitions that can
triggered by the module are shown in Table 31-28. The state diagram of the transmitter is shown in
Figure 31-27.
Figure 31-27. Receiver State Diagram
The current state of the receiver can be determined by the RE and RWU bit in the eSCI Control Register
1 (eSCI_CR1) and the RACT status bit in eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1).
The application triggers a transition described in Table 31-27 when it issues a command by writing to the
RE bit in the eSCI Control Register 1 (eSCI_CR1). The transition is triggered only if the conditions are
fulfilled. As a result of the transition the state of the receiver is changed as shown in Figure 31-27 and the
action given in Table 31-27 is executed.
Table 31-26. Receiver States
State
Indication
Description
RE RACT RWU
Idle 0 0 0 Receiver is disabled and no reception is running
Ready 1 0 0 Receiver is enabled and no reception is running
Run 1 1 0 Receiver is enabled and reception is running
Wakeup 1 — 1 Receiver is in wakeup mode
Ready
EN
start
Idle
RESET_STATE
DISDIS
done
Run
Wakeup
SLP SLP
wake0wake1
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