NXP Semiconductors PXN2020 - 1.6 Packages; 1.7 Module Features; 1.7.1 High Performance e200 z650 Core Processor (CPU)

Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
1-6 Freescale Semiconductor
– In SLEEP mode, the 16 MHz IRC can be enabled to continue to run and may be selected to
clock the RTC and API
– In SLEEP mode, the 128 kHz IRC can be enabled to run and may be selected to clock the
RTC and API
– In Sleep mode the 32 kHz XTAL can be enabled to run and may be selected to clock the
RTC and API
• Up to 32 external pins for wake-up from low power modes
• Input filters available on all wake-up pins to minimize false wakeups due to noise
• Rapid exit from low power mode with fast startup internal voltage regulator
1.6 Packages
PXN20 family members are offered in the following package types:
• 208-ball MAPBGA, 1mm ball pitch, 17mm  17mm outline for production
• 256-ball MAPBGA 1mm ball pitch 17mm  17mm outline for emulation, providing access to full
Nexus port without sacrificing GPIO functionality (not available for production)
1.7 Module Features
The following sections provide details of the modules implemented on the PXN20 family.
1.7.1 High Performance e200z650 Core Processor (CPU)
32-bit CPU built on Power Architecture
®
technology
• Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction
• Thirty-two 64-bit general-purpose registers (GPRs)
• Memory management unit (MMU) with 32-entry fully-associative translation look-aside buffer
(TLB)
• Branch processing unit
• Fully pipelined load/store unit
• 32 KB unified cache with line locking
— 4/8-way set associative
— Two 32-bit fetches per clock
— Eight-entry store buffer
— Way locking
— Supports assigning cache as instruction or data only on a per way basis
— Supports tag and data parity
• Vectored interrupt support
• Very low interrupt latency
• Reservation instructions for implementing read-modify-write constructs (internal SRAM and
flash)