e200z0 Core (Z0)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 14-11
14.3.3 e200z0 Core Complex Features not Supported on the PXN20
The PXN20 implements a subset of the e200z0 core complex features. The e200z0 core complex features
that are not supported in the PXN20 are described in Table 14-2.
14.4 Interrupt Types
The interrupts implemented on the PXN20 and the exception conditions that cause them are listed in
Table 14-3.
Table 14-2. e200z0 Features Not Supported on the PXN20
Description Function/Category
The less significant halfword of the Processor Version Register (PVR) provides the revision
level which is comprised of the following three bit fields:
Reserved = 0x00
Revision = 0x0
ID = 0x0
The more significant halfword of the Processor Version Register (PVR) provides the
processor type and version number (see Tabl e 1 4- 1).
PVR Value
Nexus registers are not accessible by code running in User or Supervisor mode. Nexus
registers can be accessed only by external tools via the Nexus port.
Debug
Table 14-3. Exceptions and Conditions
Interrupt Type
Interrupt Vector
Offset Register
Causing Conditions
System reset
none, vector to
address determined
by CRP_Z0VEC
1. Reset.
2. Debug Reset Control.
Critical Input IVOR 0
1
Non-maskable interrupt request and MSR[CE] = 1.
Machine check IVOR 1
1. Machine check error and MSR[ME] = 1.
2. Bus error (XTE) with MSR[EE] = 0 and current MSR[ME] = 1
Data Storage IVOR 2
1. Access control. (unused on e200z0)
2. Precise external termination error and MSR[EE] = 1.
Instruction
Storage
IVOR 3
1. Access control. (unused on e200z0)
2. Precise external termination error and MSR[EE] = 1.
External Input IVOR 4
1
Interrupt request and MSR[EE] = 1.
Alignment IVOR 5
1. lmw, stmw not word aligned.
2. lwarx or stwcx. not word aligned.
Program IVOR 6 Illegal, Privileged, Trap, Unimplemented Operation.
Floating-point
unavailable
IVOR 7 Unused
System call IVOR 8 Execution of the System Call (se_sc) instruction
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