NXP Semiconductors PXN2020 - 28.3.2.7 eMIOS200 Counter Register (EMIOS_CCNTR[n])

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-13
28.3.2.7 eMIOS200 Counter Register (EMIOS_CCNTR[n])
The EMIOS_CCNTR[n] register contains the value of the internal counter for eMIOS channel n. When
GPIO mode is selected or the channel is frozen, the EMIOS_CCNTR[n] register is read/write. For all other
modes, the EMIOS_CCNTR[n] is a read-only register. When entering some operation modes, this register
is automatically cleared (refer to Section 28.4.1.1, Unified Channel Modes of Operation, for details).
Table 28-9. EMIOS_CADR[n] and EMIOS_CBDR[n] Values Assignment
Operation Mode
Register Access
Write Read Write Read Alternate Read
GPIO A1, A2 A1 B1, B2 B1 —
SAIC
1
— A2B2B2 —
SAOC
1
1
In these modes, the register EMIOS_CBDR[n] is not used, but B2 can be accessed.
A2 A1 B2 B2 —
IPWM — A2 — B1 —
IPM — A2 — B1 —
DAOC A2 A1 B2 B1 —
PEA A1 A2 — B1 —
PEC
1
A1 A1 B1 B1 A2
QDEC
1
A1 A1 B2 B2 —
MC
1
A2 A1 B2 B2 —
OPWMT A1 A1B2B1 A2
MCB
1
A2 A1 B2 B2 —
OPWFMB A2 A1 B2 B1 —
OPWMCB A2 A1 B2 B1 —
OPWMB A2 A1B2B1 —
Offset: UC[n] base address + 0x0008 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RC
W
Reset0000000000000000
1
In GPIO mode or freeze action, this register is writable.
Figure 28-9. eMIOS200 Counter Register (EMIOS_CCNTR[n])