NXP Semiconductors PXN2020 - 30.4.4.4 DSI Deserialization

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-36 Freescale Semiconductor
Alternate Serialization Data Register (DSPI_ASDR) as the source of the serialized data. See
Section 30.3.2.11, DSPI DSI Serialization Data Register (DSPI_SDR), and Section 30.3.2.12, DSPI DSI
Alternate Serialization Data Register (DSPI_ASDR), for more details. The DSPI_SDR holds the latest
parallel input signal values, which are sampled at every rising edge of the system clock. The DSPI_ASDR
register is written by host software and used as an alternate source of serialized data.
A copy of the last 32-bit DSI frame shifted out of the Shift Register is stored in the DSPI DSI Transmit
Comparison Register (DSPI_COMPR). This register provides added visibility for debugging and it serves
as a reference for transfer initiation control.Section 30.3.2.13, DSPI DSI Transmit Comparison Register
(DSPI_COMPR), contains details on the DSPI_COMPR. Figure 30-21 shows the DSI Serialization logic.
Figure 30-21. DSI Serialization Diagram
30.4.4.4 DSI Deserialization
When all bits in a DSI frame have been shifted in, the frame is copied to the DSPI DSI Deserialization
Data Register (DSPI_DDR). This register presents the deserialized data as parallel output signal values.
The DSPI_DDR is memory mapped to allow host software to read the deserialized data directly. For more
information on the DSPI_DDR, refer to Section 30.3.2.14, DSPI DSI Deserialization Data Register
(DSPI_DDR). Figure 30-22 shows the DSI Deserialization logic.
When all bits in a DSI frame have been shifted in, the frame is copied to the DSPI_DDR. This register
presents the deserialized data as parallel output signal values. The DSPI_DDR is memory mapped to allow
host software to read the deserialized data directly. For more information on the DSPI_DDR, refer to
Section 30.3.2.14, DSPI DSI Deserialization Data Register (DSPI_DDR). Figure 30-22 shows the DSI
deserialization logic.
1
0
DSPI Alternate
Serialization Data Register
SOUTx
Parallel
DSI Configuration
Register
DSI Transmit
Comparison Register
Clock
Logic
0 1 • • • • • 15
Shift Register
DSI Serialization
Data Register
Control
Logic
SCKx
Inputs
PCSx
32
32
16
32
TXSS
Slave Bus Interface
32