Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 12-35
12.4.2 UTest Mode
UTest mode is a mode that customers can put the flash module in to do specific tests to check the integrity
of the Flash module.
12.4.2.1 Array Integrity Self Check
Array integrity is checked using a pre-defined address sequence (based on UT0[AIS]), and this operation
is executed on selected and unlocked blocks. The data to be read is customer-specific. Thus, a customer
can provide user code into the flash and the correct MISR value is calculated. The customer is free to
provide any random or non-random code, and a valid MISR signature is calculated. Once the operation is
completed, the result of the reads can be checked by reading the MISR value to determine if an incorrect
read or ECC detection was noted. Array integrity is controlled by the system clock, and it is required that
the Read Wait States and Address Pipeline control registers in the BIU be set to match the user-defined
frequency being used.
The array integrity check consists of the following sequence of events:
1. Enable UTest mode.
2. Select the block, or blocks to be receive array integrity check by writing ones to the appropriate
registers in LMS or HBS registers.
NOTE
Locked Blocks can be tested with array integrity if selected in LMS and
HBS.
NOTE
It is not possible to do UTest operations on the shadow block.
3. If desired, Set the UT0[AIS] bit to 1 for sequential addressing only.
NOTE
For normal integrity checks of the flash memory, sequential addressing is
recommended. If sequential addressing is selected, BIU read requests can be
done and will interrupt the array integrity sequence. Upon resuming the
Array Integrity operation will continue from where it left off. The
suspending and resuming of the array integrity operation is handled
internally by the BIU.
NOTE
If it is required to more fully check the read path (in a diagnostic mode), it
is recommend that AIS be left at 0, to use the address sequence that checks
the read path more fully, and examine read transitions. This sequence takes
more time. If this sequence is selected, it is recommended to not allow BIU
read request interruptions, as this will diminish the effectiveness of the array
integrity test, and the results will be non-deterministic.
4. Seed the MISR fields in UM0 through UM4 with the desired values.
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