NXP Semiconductors PXN2020 - 6.5 Power Supply Monitors; 6.5.1 Power-On Reset (POR); 6.5.2 Low-Voltage Monitors (LVI)

Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 6-29
6.5 Power Supply Monitors
6.5.1 Power-On Reset (POR)
The internal Power On Reset (POR) monitors the main supply input voltage (V
DDA
) and shall not release
the internal reset line until V
DDA
is above the de-assertion threshold. The POR is always enabled.
6.5.2 Low-Voltage Monitors (LVI)
The internal LVI circuits monitor when the voltage on the corresponding supply is lower than defined
values, and either assert a reset or an interrupt. All LVI circuits are enabled in run mode. In sleep mode,
LVI12 remains on. The LVIs also support hysteresis in the falling and rising trip points.
• LVI12—1.2 V supply
— The LVI12 supply monitors V
DD
and triggers a reset when it drops below the assert threshold
of the LVI12.
• LVI33—3.3 V supply
— The LVI33 monitors V
DD33
and triggers a reset when it falls below the assert level.
• LVI33SYN—3.3 V V
DDSYN
supply
— The LVI33SYN monitors V
DDSYN
and triggers a reset when it falls below the assert level.
• LVI5_VDDA—3.3 V – 5 V supply
— The LVI_VDDA monitors V
DDA
and triggers an interrupt or internal reset when it drops down
below the assert level. LVI5_VDDA is automatically disabled when VRCSEL is low.
• LVI5L_VDDA— 3.3 V – 5 V supply
— The LVIL_VDDA monitors V
DDA
and triggers an internal reset when it drops down below the
assert level.
• LVI5H_VDDA— 3.3 V – 5 V supply
— The LVIH_VDDA monitors V
DDA
and may be used to generate an internal interrupt when it
drops down below the assert level. LVI5H_VDDA is automatically disabled when VRCSEL is
low.
When a LVI5 trigger event occurs, the CRP_SOCSC[LVI5F] flag bit is set, and either a reset or an interrupt
generated, depending on the configuration of the CRP_SOCSC[LVI5IE] and CRP_SOCSC[LVIRE] bits
in the CRP. The CRP_SOCSC[LVI5RE] is always writable as long as the CRP_SOCSC[LVI5LOCK] bit
is cleared. When CRP_SOCSC[LVI5LOCK] is set, then writes to CRP_SOCSC[LVI5RE] have no effect.
The CRP_SOCSC[LVI5LOCK] bit is write-once and cleared only with POR.
There is no internal LVI monitoring of the individual V
DDE
I/O segments.