NXP Semiconductors PXN2020 - 30.5.5 Calculation of FIFO Pointer Addresses

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-62 Freescale Semiconductor
30.5.5 Calculation of FIFO Pointer Addresses
The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid
entries can be identified through a memory-mapped pointer and a memory-mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is
the transmit next pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the pop next pointer
(POPNXTPTR). Figure 30-43 illustrates the concept of first-in and last-in FIFO entries along with the
FIFO counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. See
Section 30.4.3.4, Transmit First-In First-Out (TX FIFO) Buffering Mechanism, and Section 30.4.3.5,
Receive First-In First-Out (RX FIFO) Buffering Mechanism, for details on the FIFO operation.
Figure 30-43. TX FIFO Pointers and Counter
Table 30-37. Oak Family QSPI Compatibility with the DSPI
Oak Family Control Bits
DSPI Corresponding Control Bits
Corresponding DSPI_CTARn Register Configuration
BITSE CTAS[0] DT CTAS[1] DSCK CTAS[2] DSPI_CTARn FMSZ PDT DT PCSSCK CSSCK
0 0 0 0 1111 10 0011 00 0000
0 0 1 1 1111 10 0011 user user
0 1 0 2 1111 user
1
1
Selected by user
user 00 0000
0 1 1 3 1111 user user user user
1 0 0 4 user 10 0011 00 0000
1 0 1 5 user 10 0011 user user
1 1 0 6 user user user 00 0000
1 1 1 7 user user user user user
Entry C
Entry A (first In)
– 1
Entry B
Entry D (last In)
TX FIFO base
Push TX FIFO
TX FIFO counter
Shift register SOUT
register
Transmit next
data pointer
–
–
–
–
+ 1
(TXNXTPTR)