Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
32-18 Freescale Semiconductor
rx_count -- // decrease the rx counter
if (rx_count ==1) // 2nd last byte to be read ?
bit 4, IBCR = 1 // disable ACK
if (rx_count == 0) // last byte to be read ?
bit 6, IBCR = 0 // generate stop signal
else
data_received = IBDR // read RX data and store
32.5.1.5 Generation of Repeated START
At the end of data transfer, if the master wants to remain communicating on the bus, it can generate another
START signal followed by another slave address without first generating a STOP signal. A program
example is as shown.
bit 5, IBCR = 1 // generate another start ( restart)
IBDR == calling_address // transmit the calling address
32.5.1.6 Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) must be tested to check if
a calling of its own address has been received. If IAAS is set, software sets the transmit/receive mode
select bit (TX bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears IAAS
automatically. IAAS is read as set when it is from the interrupt at the end of the address cycle where an
address match occurred. Interrupts resulting from subsequent data transfers have IAAS cleared. A data
transfer may be initiated by writing information to IBDR for slave transmits or dummy reading from IBDR
in slave receive mode. The slave drives SCL low in-between byte transfers SCL is released when the IBDR
is accessed in the required mode.
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the
next byte of data. Setting RXAK means an end of data signal from the master receiver, after which it must
be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL
line so the master can generate a STOP signal.
32.5.1.7 Arbitration Lost
If several masters try to engage the bus simultaneously, one master wins and the others lose arbitration.
The devices that lost arbitration are immediately switched to slave receive mode by the hardware. Their
data output to the SDA line is stopped, but SCL remains generated until the end of the byte during which
arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL = 1
and MS = 0. If one master attempts to start transmission while the bus is being engaged by another master,
the hardware inhibits the transmission, switches the MS bit from 1 to 0 without generating a STOP
condition, generates an interrupt to CPU, and sets the IBAL to indicate that the attempt to engage the bus
is failed. When considering these cases, the slave service routine should test the IBAL first and the
software should clear the IBAL bit if it is set.
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