Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
27-4 Freescale Semiconductor
Detailed signal descriptions for the MLB peripheral can be found in Table 27-4.
:
27.3 Memory Map and Register Description
27.3.1 Memory Map
Table 27-5 shows the MLB configuration registers. Table 27-6 shows the channel configuration registers
for each channel within the MLB. Table 27-7 shows the overall memory map for the MLB.
Table 27-3. Signal Properties
Signal Port SIU_PCR Register Function I/O Reset Pull
MLBCLK PK0 SIU_PCR144 MLB Clock I 0 Down
MLBSIG PK1 SIU_PCR145 MLB Signal (control/status) I/O 0 Down
MLBDAT PK2 SIU_PCR146 MLB Data I/O 0 Down
Table 27-4. MLB—Detailed Signal Descriptions
Signal I/O Description
MLBCLK I MLB Clock.
State Meaning Asserted/Negated—Supports a 256Fs, 512Fs or 1024Fs clock input from the MLB
controller.
Timing Assertion/Negation—Supports maximum frequency of 49.2 MHz with a 48 kHz sample
rate.
MLBDAT I/O MLB Data
State Meaning Asserted/Negated—MLB data for serial receive/transmit channel data.
Timing Assertion/Negation—Input registered on the falling edge of MLBCLK. Output driven
from the rising edge of MLBCLK.
MLBSIG I/O MLB Signal (control/status)
State Meaning Asserted/Negated—MLB signal information for serial transmit channel commands,
serial receive channel responses, and logical channel address information.
Timing Assertion/Negation—Input registered on the falling edge of MLBCLK. Output driven
from the rising edge of MLBCLK.
Table 27-5. Configuration Registers
Offset from
MLB_BASE
(
0xC3F8_4000)
Name Access
0x0000_0000 DCCR—Device Control Configuration Register R/W
0x0000_0004 SSCR—System Status Configuration Register R/W
0x0000_0008 SDCR—System Data Configuration Register R
0x0000_000C SMCR—System Mask Configuration Register R/W
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