Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-61
30.5.4 Oak Family Compatibility with the DSPI
Table 30-37 shows the translation of commands written to the TX FIFO command halfword with
commands written to the Command Ram of the Oak family QSPI. The table illustrates how to configure
the DSPI_CTARn registers to match the default cases for the possible combinations of the Oak Family
Control Bits in its command RAM. The defaults for the Oak Family are based on a system clock of
40 MHz. All delay variables below generate the same delay, or as close as possible, from the DSPI
100 MHz system clock that an Oak Family part would generate from its 40 MHz system clock. For other
system clock frequencies, the customer can recompute the values using Section 30.5.3, Delay Settings.
• For BITSE = 0 8 bits per transfer
• For DT = 0 0.425 µs delay: For this value, the closest value in the DSPI is 0.480 µs
• For DSCK = 0 1/2 SCK period: For this value, the value for the DSPI is 20 ns
Table 30-36. Delay Values
Delay Prescaler Values
1357
Delay Scaler Values
2 20.0 ns 60.0 ns 100.0 ns 140.0 ns
4 40.0 ns 120.0 ns 200.0 ns 280.0 ns
8 80.0 ns 240.0 ns 400.0 ns 560.0 ns
16 160.0 ns 480.0 ns 800.0 ns 1.1 s
32 320.0 ns 960.0 ns 1.6 s2.2 s
64 640.0 ns 1.9 s3.2 s4.5 s
128 1.3 s3.8 s6.4 s9.0 s
256 2.6 s7.7 s 12.8 s 17.9 s
512 5.1 s 15.4 s 25.6 s 35.8 s
1024 10.2 s 30.7 s 51.2 s 71.7 s
2048 20.5 s 61.4 s 102.4 s 143.4 s
4096 41.0 s 122.9 s 204.8 s 286.7 s
8192 81.9 s 245.8 s 409.6 s 573.4 s
16384 163.8 s 491.5 s 819.2 s 1.1 ms
32768 327.7 s 983.0 s 1.6 ms 2.3 ms
65536 655.4 s 2.0 ms 3.3 ms 4.6 ms
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