NXP Semiconductors PXN2020 - 25.3.4.14 Opcode;Pause Duration Register (OPD)

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-22 Freescale Semiconductor
25.3.4.14 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit OPCODE and 16-bit pause duration
(PAUSE_DUR) fields used in transmission of a PAUSE frame. The OPCODE field is a constant value,
0x0001. When another node detects a PAUSE frame, that node pauses transmission for the duration
specified in the pause duration field. This register is not reset and must be initialized by the user. Refer to
Section 25.4.10, Full Duplex Flow Control, for information on using the OPD register.
Offset: FEC_BASE + 0x00E8 Access: User read/write
0123456789101112131415
R
PADDR2
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TYPE
W
Reset1000100000001000
Figure 25-13. Physical Address Upper Register (PAUR)
Table 25-16. PAUR Field Descriptions
Field Description
PADDR2 Bytes 4 (bits 0:7) and 5 (bits 8:15) of the 6-byte individual address to be used for exact match, and the
Source Address field in PAUSE frames.
TYPE The type field is used in PAUSE frames. These bits are a constant, 0x8808.
Offset: FEC_BASE + 0x00EC Access: User read/write
0123456789101112131415
ROPCODE
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PAUSE_DUR
W
ResetUUUUUUUUUUUUUUUU
Figure 25-14. Opcode/Pause Duration Register (OPD)