NXP Semiconductors PXN2020 - 34.3.2.34 Power Down Exit Delay Register (PDEDR); 34.3.2.35 Precision Channel n Data Register (PRECDATAREGn)

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
34-38 Freescale Semiconductor
34.3.2.34 Power Down Exit Delay Register (PDEDR)
The PDEDR register specifies the delay between the power-down reset and the start of the next conversion.
34.3.2.35 Precision Channel n Data Register (PRECDATAREGn)
The PRECDATAREGn registers provide conversion results for the group 0 channel (channels 0–31) data
registers. Each data register gives also some information regarding the corresponding result. One
PRECDATAREGn register is provided for each channel.
Address: ADC_BASE + 0x00C8 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000
PDED
W
Reset0000000000000000
Figure 34-35. Power Down Exit Delay Register (PDEDR)
Table 34-37. PDEDR Field Descriptions
Field Description
PDED The delay between the power down bit MCR[PWDN] reset and the start of the next conversion.
Address: See Tabl e 34 -1. Access: User read/write
0123456789101112131415
R000000000000
VALID OVERW RESULT
W
Reset0000000000000 0 00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000
CDATA
W
Reset0000000000000 0 00
Figure 34-36. Precision Channel n Data Register (PRECDATAREGn)
Table 34-38. PRECDATAREGn Field Descriptions
Field Description
VALID Used to notify when the data is valid (a new value has been written). It is automatically cleared when data is
read.
OVERW Overwrite data. Used to notify when a conversion data is overwritten by a newer result.The new data is written
or discarded according to the OWREN bit of MCR register.