Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-3
10.1.2 Interrupt Controller Features
• Supports 308 peripheral and eight software-settable interrupt request sources.
• Each interrupt source can be steered by software to processor 0 (Z6), processor 1 (Z0), or both
processors interrupt request outputs.
NOTE
By default, processor 0 (Z6) receives all interrupt requests, so backward
compatibility with single processor systems is maintained.
• 9-bit unique vector for each interrupt request source in hardware vector mode.
• Each interrupt source can be programmed to one of 16 priorities
• Preemption
— Preemptive prioritized interrupt requests to processor
— ISR at a higher priority preempts ISRs or tasks at lower priorities
— Automatic pushing or popping of preempted priority to or from a LIFO
— Ability to modify the ISR or task priority; modifying the priority can be used to implement the
priority ceiling protocol for accessing shared resources.
• Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to
processor.
10.1.3 Modes of Operation
The interrupt controller has two handshaking modes with the processor: software vector mode and
hardware vector mode. The state of the hardware vector enable bit, INTC_MCR[HVEN_PRCn],
independently determines which mode is used for each CPU.
In debug mode the interrupt controller operation is identical to its normal operation of software vector
mode or hardware vector mode.
10.1.3.1 Software Vector Mode
In software vector mode, as shown in Figure 10-2, the CPU branches to a common interrupt exception
handler whose location is determined by an address derived from special purpose registers IVPR and
IVOR4. The interrupt exception handler reads the INTC_IACKR to determine the vector of the interrupt
request source.
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