FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-128 Freescale Semiconductor
26.6.9.5 FIFO Almost-Full Interrupt Generation
If the fifo fill level FLA (FLB) is updated after a frame reception and exceeds the FIFO watermark level
WM, i.e. FLA>WM
A
(FLB>WM
B
), then the FIFO almost-full interrupt flag GIFER[FAFAIF]
(GIFER[FAFBIF]) is asserted.If the periodic timer expires, and FIFOA (FIFOB) is not empty, i.e. FLA>0
(FLB>0), then the FIFO almost-full interrupt flag GIFER[FAFAIF] (GIFER[FAFBIF]) is asserted.
26.6.9.6 FIFO Overflow Error Generation
If the FIFOA (FIFOB) is full, i.e. FLA=FIFO_DEPTH
A
(FLB=FIFO_DEPTH
B
) and the conditions for a
FIFO reception as described in Section 26.6.9.4, FIFO Reception, are fulfilled, then the fifo overflow error
flag CHIERFR[FOVA_EF] (CHIERFR[FOVB_EF]) is asserted.
26.6.9.7 FIFO Message Access
The FIFOA (FIFOB) contains valid messages if the FIFO fill level FLA (FLB) is greater than 0. The
Receive FIFO A Read Index Register (RFARIR) (Receive FIFO B Read Index Register (RFBRIR))
pointing to a message buffer with valid content and the oldest frames stored in the FIFO.
If the FIFO fill level FLA (FLB) is 0, than the FIFOA (FIFOB) contains no valid messages and the Receive
FIFO A Read Index Register (RFARIR) (Receive FIFO B Read Index Register (RFBRIR)) pointing to a
message buffer with invalid content. In this case the application must not read data from the FIFO.
To access the oldest message in the FIFOA (FIFOB), the application first reads the read index RDIDX out
of the Receive FIFO A Read Index Register (RFARIR) (Receive FIFO B Read Index Register (RFBRIR)).
This read index points to the message buffer header field of the oldest message buffer that contains valid
received message data. The application can access the message data as described in Section 26.6.3.3,
Receive FIFO. When the application has read the message buffer data and status information, it can update
the FIFO as described in Section 26.6.9.8, FIFO Update.
26.6.9.8 FIFO Update
The application updates the FIFOA (FIFOB) by writing a pop count value pc different from 0 to the
PCA (PCB) field in the Receive FIFO Fill Level and POP Count Register (RFFLPCR).
As a result of the this operation, the controller removes the oldest pc entries from FIFOA (FIFOB).
If the specified pop count value pc is greater than the current fill level fl provided in FLA (FAB) field, then
only fl entries are removed from the FIFOA (FIFOB), the remaining fl-pc requested pop operations are
discarded without any notification. In this case FIFOA (FIFOB) is empty after the update operation.
The read index in the Receive FIFO A Read Index Register (RFARIR) (Receive FIFO B Read Index
Register (RFBRIR)) is incremented by the number of removed items. If the read index reaches the top of
the FIFO, it wraps around to the FIFO start index defined in Receive FIFO Start Index Register (RFSIR)
automatically.
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