Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-18 Freescale Semiconductor
25.3.4.9 MIB Control Register (MIBC)
The MIBC is a read/write register used to provide control of and to observe the state of the MIB block.
This register is accessed by user software if there is a need to disable the MIB block operation. For
example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all
the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See Table 25-3
for the locations of the MIB counters.
25.3.4.10 Receive Control Register (RCR)
The RCR is programmed by the user. The RCR controls the operational mode of the receive block and
1
Note: Observe maximum system clock frequency when programming MII_SPEED.
Offset: FEC_BASE + 0x0064 Access: User read/write
0123456789101112131415
RMIB_
DISA
BLE
MIB_
IDLE
00000000000000
W
Reset1100000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Figure 25-9. MIB Control Register (MIBC)
Table 25-12. MIBC Field Descriptions
Field Description
MIB_DISABLE A read/write control bit. If set, the MIB logic halts and does not update any MIB counters.
MIB_IDLE A read-only status bit. If set, the MIB block is not currently updating any MIB counters.
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