Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-19
should be written only when ECR[ETHER_EN] = 0 (initialization time).
Offset: FEC_BASE + 0x0084 Access: User read/write
0123456789101112131415
R 00000
MAX_FL
W
Reset0000010111101 110
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000
FCE
BC_
REJ
PROM
MII_
MODE
DRT LOOP
W
Reset0000000000000 000
Figure 25-10. Receive Control Register (RCR)
Table 25-13. RCR Field Descriptions
Field Description
0–4 Reserved, should be cleared.
MAX_FL Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC
at the end of the frame. Transmit frames longer than MAX_FL cause the BABT interrupt to occur. Receive
frames longer than MAX_FL cause a BABR interrupt and sets the LG bit in the end-of-frame receive buffer
descriptor. You can program the default value to 1518 or 1522 (if VLAN tags are supported).
16–25 Reserved, should be cleared.
FCE Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
transmitter stops transmitting data frames for a given duration.
BC_REJ Broadcast frame reject. If asserted, frames with DA (destination address) = FF_FF_FF_FF_FF_FF is
rejected unless the PROM bit is set. If both BC_REJ and PROM = 1, then frames with broadcast DA is
accepted and the M (MISS) bit is set in the receive buffer descriptor.
PROM Promiscuous mode. All frames are accepted regardless of address matching.
MII_MODE Media independent interface mode. Selects external interface mode. Setting this bit to one selects MII mode,
setting this bit equal to zero selects 7-wire mode (used only for serial 10 Mbps). This bit controls the interface
mode for both transmit and receive blocks.
DRT Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half
duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
LOOP Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit output
signals are not asserted. The system clock is substituted for the FEC_TX_CLK when LOOP is asserted. DRT
must be set to zero when asserting LOOP.
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