Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-11
28.3.2.3 eMIOS200 Output Update Disable Register (EMIOS_OUDR)
28.3.2.4 eMIOS200 Disable Channel Register (EMIOS_UCDIS)
Offset: EMIOS_BASE + 0x0008 Access: User read/write
0123456789101112131415
R
OU31 OU30 OU29 OU28 OU27 OU26 OU25 OU24 OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OU15 OU14 OU13 OU12 OU11 OU10 OU9 OU8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0
W
Reset0000000000000000
Figure 28-5. eMIOS200 Output Update Disable Register (EMIOS_OUDR)
Table 28-7. EMIOS_OUDR Field Descriptions
Field Description
OU[31:0] Channel [n] Output Update Disable Bits. When running MCB mode or an output mode, values are written to
registers A2 and B2. OU[n] bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit
controls one channel.
0 Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the next period.
Unless stated otherwise, transfer occurs immediately.
1 Transfers disabled.
Note: The PXN21 implements all 32 channels, comprising bits OU31 through OU0. The PXN20 implements only
24 channels, comprising bits OU23 through OU0.
Offset: EMIOS_BASE + 0x000C Access: User read/write
0123456789101112131415
R
UCDIS[31:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
UCDIS[15:0]
W
Reset0000000000000000
Figure 28-6. eMIOS200 Enable Channel Register (EMIOS_UCDIS)
Table 28-8. EMIOS_UCDIS Field Descriptions
Field Description
UCDIS[31:0] Enable Channel [n] Bit. The UCDIS[n] bit is used to disable each of the unified channels by stopping its
respective clock.
0 UC [n] enabled.
1 UC [n] disabled.
Note: The PXN21 implements all 32 channels, comprising bits UCDIS31 through UCDIS0. The PXN20
implements only 24 channels, comprising bits UCDIS23 through UCDIS0.
To Next Page
Loading...
