NXP Semiconductors PXN2020 - 5.3 Clock Dividers; 5.3.1 System Clock Select; 5.3.2 System Clock Dividers; 5.3.3 External Bus Clock (CLKOUT) Divider

System Clock Description
PXN20 Microcontroller Reference Manual, Rev. 1
5-8 Freescale Semiconductor
Figure 5-3. Detailed Clock Gating Scheme
5.3 Clock Dividers
5.3.1 System Clock Select
The source for the system clock can be selected by the SYSCLKSEL field of the SIU system clock register
(SIU_SYSCLK) to be the 16 MHz IRC, the 4 – 40 MHz XTAL, or the FMPLL.
5.3.2 System Clock Dividers
The system clock dividers can be programmed to create a system clock, which is created from the selected
clock source divided by 1, 2, 4, 8, or 16, based on the setting of the SYSCLKDIV field in the SIU system
clock register (SIU_SYSCLK).
5.3.3 External Bus Clock (CLKOUT) Divider
The system clock divided by 1, 2, 4, or 8 based on the settings of the ECDF bit field in the SIU external
clock control register (SIU_ECCR). The reset value of ECDF selects a CLKOUT frequency of one half of
the system clock frequency.
ipg_clk_s
HLTn
HLTACKn
Halt
control
ips_module_en
Bus interface
(Memory mapped registers)
MDIS
Core
halt
ipg_clk
Always clocked logic
halt
DOZE
halt
Logic
ipg_stop_ack
ipg_stop
ipg_clk
(Tied V
SS
)
Idle
&
&
halt
ipg_clk
Protocol interface
(e.g., CAN, FlexRay, etc.)
<other>_clk
(e.g., osc_clk)
Clock gate
ipg_clk_enable