System Clock Description
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 5-7
Figure 5-2. PXN20 System Clock Architecture
System
Clock
Selector
System clock
Clock Monitor Unit
FMPLL
32_kHz_XTAL
128_kHz_IRC
1 to
1: Dividers: 1, 2, 4, 8, 16
2: Dividers: 1, 2, 4, 8
3: Dividers: 1, 2, 4
1 to 8
2
1 to 8
2
2
PLL_Clk
116 MHz
4 – 40_MHz_XTAL
16_MHZ_IRC
Peripheral
Set 1
Core,
Platform
Peripheral
Set 2
Peripheral
Set 3
Peripheral
Set 4
IOP
FEC
MLB
DIM
API/RTC
2
CLKOUT
Watchdog
CLKOUT
Selector
1 to 16
1
1 to 16
1
1 to 4
3
4 – 40_MHz_XTAL
16_MHZ_IRC
System clock
2
16
1
FlexRay
1 to 8
2
1 to 8
2
1 to 8
2
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