NXP Semiconductors PXN2020 - 27.4.1 Clocking Requirements; 27.4.1.1 Reset; 27.4.2 Interrupts

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
27-28 Freescale Semiconductor
serial format required by the MLB interface. Data is transferred over the MLB in quadlets (32-bit words).
The MLB protocol supports as many as 32 quadlets per frame.
27.4.1 Clocking Requirements
The system clock (SYS_CLK) requirements for operation are shown in Table 27-23.
27.4.1.1 Reset
Soft reset of the physical and logical channel blocks is provided via the DDCE[MRS] bit.
Hard reset of the physical and logical channel blocks is enabled via the DCCR[MHRE] bit. When set,
reception of the global or device system reset commands resets the physical and link layers.
27.4.2 Interrupts
The MLB module generates 18 different interrupts, which are summarized in Table 27-24. For more
information on interrupts, please seeChapter 10, Interrupts and Interrupt Controller (INTC).
Table 27-23. Minimum MediaLB System Clock Requirements
Fs MLBCLK Minimum System Clock Speed
44.1 kHz 256 FS 12 MHz
512 FS 23 MHz
1024 FS 46 MHz
48.0 kHz 256 FS 13 MHz
512 FS 25 MHz
1024 FS 50 MHz
48.1 kHz 256 FS 13 MHz
512 FS 25 MHz
1024 FS 50 MHz
Table 27-24. MLB Interrupts
Interrupt Name
PXN20
Interrupt Vector
Interrupt Flag Bits Interrupt Mask Bits
MLB Channel Interrupt 95 CSCR0[20:31]
to
CSCR15[20:31]
CECR0[9:15]
to
CECR15[9:15]
MLB System Interrupt 96 SSCR[25:31] SMCR[25:31]
MLB Logical Channel 0 Interrupt 97 CSCR0[20:31] CECR0[9:15]
MLB Logical Channel 1 Interrupt 98 CSCR1[20:31] CECR1[9:15]
MLB Logical Channel 2 Interrupt 99 CSCR2[20:31] CECR2[9:15]
MLB Logical Channel 3 Interrupt 100 CSCR3[20:31] CECR3[9:15]