Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-37
Channel-priority errors are identified within a group after that group has been selected as the active group.
For the example, all of the channel priorities in group 1 are unique, but some of the channel priorities in
group 0 are the same:
1. The DMA is configured for fixed-group and fixed-channel arbitration modes.
2. Group 1 is the highest priority and all channels are unique in that group.
3. Group 0 is the next highest priority and has two channels with the same priority level.
4. If group 1 has any service requests, those requests are executed.
5. After all of group 1 requests have completed, group 0 becomes the next active group.
6. If group 0 has a service request, then an undefined channel in group 0 is selected and a
channel-priority error will occur.
7. This repeats until the all of group 0 requests have been removed or a higher priority group 1 request
comes in.
In this sequence, for item 2, the DMA acknowledge lines assert only if the selected channel is requesting
service via the DMA peripheral request signal. If interrupts are enabled for all channels, the user receives
an error interrupt, but the channel number for the EDMA_ER and the error interrupt request line are
undetermined because they reflect the undefined channel. A group-priority error is global and any request
in any group causes a group-priority error.
If priority levels are not unique, the highest (channel/group) priority that has an active request is selected,
but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the
DMA engine. The hardware service request handshake signals, error interrupts, and error reporting are
associated with the selected channel.
24.5.3 DMA Request Assignments
The assignments between the DMA requests from the modules to the channels of the eDMA are shown in
Table 24-22. The source column is written in C language syntax. The syntax is
module_instance.register[bit].
Table 24-22. DMA Request Summary for eDMA
DMA Request Channel Source Description
DMA_MUX_CHCONFIG0_SOURCE 0 DMA_MUX.CHCONFIG0[SOURCE] DMA MUX channel 0 source
DMA_MUX_CHCONFIG1_SOURCE 1 DMA_MUX.CHCONFIG1[SOURCE] DMA MUX channel 1 source
DMA_MUX_CHCONFIG2_SOURCE 2 DMA_MUX.CHCONFIG2[SOURCE] DMA MUX channel 2 source
DMA_MUX_CHCONFIG3_SOURCE 3 DMA_MUX.CHCONFIG3[SOURCE] DMA MUX channel 3 source
DMA_MUX_CHCONFIG4_SOURCE 4 DMA_MUX.CHCONFIG4[SOURCE] DMA MUX channel 4 source
DMA_MUX_CHCONFIG5_SOURCE 5 DMA_MUX.CHCONFIG5[SOURCE] DMA MUX channel 5 source
DMA_MUX_CHCONFIG6_SOURCE 6 DMA_MUX.CHCONFIG6[SOURCE] DMA MUX channel 6 source
DMA_MUX_CHCONFIG7_SOURCE 7 DMA_MUX.CHCONFIG7[SOURCE] DMA MUX channel 7 source
DMA_MUX_CHCONFIG8_SOURCE 8 DMA_MUX.CHCONFIG8[SOURCE] DMA MUX channel 8 source
To Next Page
Loading...
