Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-20 Freescale Semiconductor
25.3.4.11 Transmit Control Register (TCR)
The TCR is read/write and is written by the user to configure the transmit block. This register is cleared at
system reset. Bits 29 and 30 should be modified only when ECR[ETHER_EN] = 0.
Offset: FEC_BASE + 0x00C4 Access: User read/write
01234567891011 12131415
R0 0000000000 0 0 000
W
Reset00000000000 0 0 000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
00000000000
RFC_
PAU SE
TFC_
PAUS E
FDEN HBC GTS
W
Reset00000000000 0 0 000
Figure 25-11. Transmit Control Register (TCR)
Table 25-14. TCR Field Descriptions
Field Description
0–26 Reserved, should be cleared.
RFC_PAUSE Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause
frame has been received and the transmitter is paused for the duration defined in this pause frame. This bit
is automatically cleared when the pause duration is complete.
TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC stops
transmitting data frames after the current transmission is complete. At this time, the GRA interrupt in the EIR
register is asserted. With transmission of data frames stopped, the MAC transmits a MAC Control PAUSE
frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. Note that if the
transmitter is paused due to user assertion of GTS or reception of a PAUSE frame, the MAC may still transmit
a MAC Control PAUSE frame.
FDEN Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. This bit
should only be modified when ETHER_EN is deasserted.
HBC Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HB bit in
the status register is set if the collision input does not assert within the heartbeat window. This bit should only
be modified when ETHER_EN is deasserted.
GTS Graceful transmit stop. When this bit is set, the MAC stops transmission after any frame that is currently being
transmitted is complete and the GRA interrupt in the EIR register is asserted. If frame transmission is not
currently underway, the GRA interrupt is asserted immediately. Once transmission has completed, a “restart”
can be accomplished by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted. If an
early collision occurs during transmission when GTS = 1, transmission stops after the collision. The frame is
transmitted again once GTS is cleared. Note that there may be old frames in the transmit FIFO that are
transmitted when GTS is reasserted. To avoid this deassert ECR[ETHER_EN] following the GRA interrupt.
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