NXP Semiconductors PXN2020 - 28.3.2.10 eMIOS200 Alternate A Register (EMIOS_ALTA[n]); 28.4 Functional Description; 28.4.1 Unified Channel (UC)

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-20 Freescale Semiconductor
28.3.2.10 eMIOS200 Alternate A Register (EMIOS_ALTA[n])
The EMIOS_ALTA[n] register provides an alternate read-only address to access A2 channel registers in
PEC and WPTA modes only. If EMIOS_CADR[n] register is used with EMIOS_ALTA[n], both A1 and
A2 registers can be accessed in these modes.
28.4 Functional Description
The three types of channels of the eMIOS200 can operate in the modes as listed in Table 28-1.
The eMIOS200 provides independently operating unified channels (UC) that can be configured and
accessed by a host MCU. On the PXN21, as many as five time bases can be shared by the channels through
five counter buses. On the PXN20, as many as four time bases can be shared by the channels through four
counter buses. Each unified channel can generate its own time base.
The eMIOS200 block is reset at positive edge of the clock (synchronous reset). All registers are cleared
on reset.
28.4.1 Unified Channel (UC)
Figure 28-13 shows the unified channel block diagram. Each unified channel consists of:
• Counter bus selector, which selects the time base to be used by the channel for all timing functions
• A programmable clock prescaler
• Two double buffered data registers, A and B, that allow as many as two input capture and/or output
compare events to occur before software intervention is needed
• Two comparators (equal only), A and B, which compare the selected counter bus with the value in
the data registers
• Internal counter, which can be used as a local time base or to count input events
• Programmable input filter, which ensures that only valid pin transitions are received by channel
• Programmable input edge detector, which detects the rising, falling or either edges
• An output flip-flop, which holds the logic level to be applied to the output pin
• eMIOS200 status and control register
UC[n] base address + 0x0014 Access: User read/write
0123456789101112131415
R00000000 ALTA
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RALTA
W
Reset0000000000000000
Figure 28-12. eMIOS200 Alternate A Register (EMIOS_ALTA[n])