Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-21
25.3.4.12 Physical Address Low Register (PALR)
The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit MAC
address used in the address recognition process to compare with the DA (destination address) field of
receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte
source address field when transmitting PAUSE frames. This register is not reset and must be initialized by
the user.
25.3.4.13 Physical Address Upper Register (PAUR)
The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the 48-bit MAC
address used in the address recognition process to compare with the DA (destination address) field of
receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source
Address field when transmitting PAUSE frames. Bits 16:31 of PAUR contain a constant TYPE field
(0x8808) used for transmission of PAUSE frames.This register is not reset, and bits 0:15 must be initialized
by the user. Refer to Section 25.4.10, Full Duplex Flow Control, for information on using the TYPE field.
Offset: FEC_BASE + 0x00E4 Access: User read/write
0123456789101112131415
R
PADDR1
W
Reset U
1
1
“U” signifies a bit that is uninitialized. Refer to the Preface of the book.
UUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PADDR1
W
ResetUUUUUUUUUUUUUUUU
Figure 25-12. Physical Address Low Register (PALR)
Table 25-15. PALR Field Descriptions
Field Description
PADDR1 Bytes 0 (bits 0:7), 1 (bits 8:15), 2 (bits 16:23) and 3 (bits 24:31) of the 6-byte individual address to be used
for exact match, and the Source Address field in PAUSE frames.
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