NXP Semiconductors PXN2020 - 30.3.2.4 DSPI Status Register (DSPI_SR)

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-16 Freescale Semiconductor
30.3.2.4 DSPI Status Register (DSPI_SR)
The DSPI_SR contains status and flag bits. The bits reflect the status of the DSPI and indicate the
occurrence of events that can generate interrupt or DMA requests. Software can clear a flag bit in the
DSPI_SR by writing a 1 to it. Writing a 0 to a flag bit has no effect.
NOTE
This register cannot be written in module disable mode, owing to the use of
power saving mechanisms.
NOTE
When generating DSPI bit frames in Continuous Peripheral Chip Select
mode (DSPIx_PUSHR[CONT=1]) and when changing DSPIx_CTARn bit
fields between frames, adhere to the following conditions, as they can
generate error if:
• If DSPIx_CTARn[CPHA]=1, DSPIx_MCR[CONT_SCKE = 0], and
DSPIx_CTARn[CPOL, CPHA, PCSSCK or PBR] change between
frames.
• If DSPIx_CTARn[CPHA]=0 or DSPIx_MCR[CONT_SCKE = 1] and
any bit field of DSPIx_CTARn changes between frames except
DSPIx_CTARn[PBR].
Offset: DSPI_BASE + 0x002C Access: User read-only
0 1 2 3 4 5 6 7 8 9 101112131415
R
TCF
TXRXS 0
EOQF TFUF
0
TFFF
00000
RFOF
0
RFDF
0
W
Reset0 0 00000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TXCTR TXNXTPTR RXCTR POPNXTPTR
W
Reset0 0 00000000000000
Figure 30-6. DSPI Status Register (DSPI_SR)