NXP Semiconductors PXN2020 - 8.3.2.44 Masked Parallel GPIO Pin Data Output Register 8 (SIU_MPGPDO8); 8.3.2.45 Masked Parallel GPIO Pin Data Output Register 9 (SIU_MPGPDO9)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-56 Freescale Semiconductor
8.3.2.44 Masked Parallel GPIO Pin Data Output Register 8 (SIU_MPGPDO8)
The SIU_MPGPDO8 register contains the masked parallel GPIO pin data output for PJ[0:15].
Writes to this register are coherent with registers SIU_GPDO128_131, SIU_GPDO132_135,
SIU_GPDO136_139, and SIU_GPDO140_143.
8.3.2.45 Masked Parallel GPIO Pin Data Output Register 9 (SIU_MPGPDO9)
The SIU_MPGPDO8 register contains the masked parallel GPIO pin data output for PK[0:10].
Writes to this register are coherent with registers SIU_GPDO144_147, SIU_GPDO148_151, and
SIU_GPDO152_154.
Offset: SIU_BASE + 0xC9C Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PH_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PH[0:15]
Reset0000000000000000
Figure 8-51. Masked Parallel GPIO Pin Data Output Register 7 (SIU_MPGPDO7)
Offset: SIU_BASE + 0x0CA0 Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PJ_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PJ[0:15]
Reset0000000000000000
Figure 8-52. Masked Parallel GPIO Pin Data Output Register 8 (SIU_MPGPDO8)