EasyManua.ls Logo

NXP Semiconductors PXN2020 - 8.3.2.47 Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL); 8.3.2.48 Masked Serial GPO Register for DSPI_B High (SIU_DSPIBH)

NXP Semiconductors PXN2020
1376 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-58 Freescale Semiconductor
8.3.2.47 Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL)
The SIU_DSPIAL register allows any combination of bits in the bottom half of the 32-bit serialized data
frame from DSPI_A to be updated with a single 32-bit write operation, while allowing other bits to
maintain their previous state. This is accomplished by writing a 16-bit masked value coherently with an
update value contained in a 16-bit output field, and only updating those bits in the output register for which
the corresponding mask bit is set.
8.3.2.48 Masked Serial GPO Register for DSPI_B High (SIU_DSPIBH)
The SIU_DSPIBH register allows any combination of bits in the top half of the 32-bit serialized data frame
from DSPI_B to be updated with a single 32-bit write operation, while allowing other bits to maintain their
previous state. This is accomplished by writing a 16-bit masked value coherently with an update value
contained in a 16-bit output field, and only updating those bits in the output register for which the
corresponding mask bit is set.
Offset: SIU_BASE + 0x0D04 Access: User read/write
0123456789101112131415
R
MASK
15
MASK
14
MASK
13
MASK
12
MASK
11
MASK
10
MASK
9
MASK
8
MASK
7
MASK
6
MASK
5
MASK
4
MASK
3
MASK
2
MASK
1
MASK
0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DATA
15
DATA
14
DATA
13
DATA
12
DATA
11
DATA
10
DATA
9
DATA
8
DATA
7
DATA
6
DATA
5
DATA
4
DATA
3
DATA
2
DATA
1
DATA
0
W
Reset0000000000000000
Figure 8-55. Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL)
Table 8-34. SIU_DSPIAL Field Descriptions
Field Description
MASKn Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_A.
0 The previous value defined by GPO for DSPI_A is maintained.
1 The corresponding GPO for DSPI_A is written with the value defined by the DATAn field.
DATAn Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_A output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.

Table of Contents

Related product manuals