NXP Semiconductors PXN2020 - 13.1.2 Overview

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-2 Freescale Semiconductor
Figure 13-1. e200z6 Block Diagram
13.1.2 Overview
The e200z6 core integrates the following:
• Integer execution unit
• Branch control unit
• Instruction fetch and load/store units
• Multi-ported register file capable of sustaining three read and two write operations per clock.
CPU
Control Logic
Load/
32 KB
Cache
Data
Memory
Management
Unit
Address
Store
Unit
Control
Instruction Unit
Address
Branch
Unit
PC
Unit
Instruction Buffer
GPRs
CR
SPR
Multiply
Unit
Bus Interface Unit
Control
32
64
Data Out
64
64
Signal
Processing
OnCE/NEXUS 1/
Control Logic
Engine
(SPE APU)
Unified
Integer
Execution
Unit
Data In
64
CTR
XER
LR
(64-bit)
NEXUS 3