NXP Semiconductors PXN2020 - 36.7.9.7 IEEE 1149.1 (JTAG) RD;WR Sequences

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-101
Note that T0, A0, D0 are the least significant bits where:
•Tx = TCODE number (fixed)
•Sx = Source processor (fixed)
•Zx = Data size (fixed)
•Ax = Unique portion of the address (variable)
•Dx = Write data (variable 8-bit, 16-bit, or 32-bit)
36.7.9.7 IEEE 1149.1 (JTAG) RD/WR Sequences
This section contains example JTAG/OnCE sequences used to access resources.
36.7.9.7.1 JTAG Sequence for Accessing Internal Nexus Registers
Table 36-64. Direct Write Message Example (12 MDO / 2 MSEO)
Clock
MDO[11:0]
MSEO[1:0] State
11109876543210
0 XXXXXXXXXXXX 1 1 Idle (or end of last
message)
1 Z1Z0S3S2S1S0T5T4T3T2T1T0 0 0 Start Message
2 0 0 0 0 0 0 0 A3 A2 A1 A0 Z2 0 1 End Packet
3 X X X X D7D6D5D4D3D2D1D0 1 1 End Packet/End
Message
Table 36-65. Accessing Internal Nexus2+ Registers via JTAG/OnCE
Step # TMS Pin Description
11IDLE SELECT-DR_SCAN
2 0 SELECT-DR_SCAN  CAPTURE-DR (Nexus command register value loaded in shifter)
3 0 CAPTURE-DR
 SHIFT-DR
4 0 (7) TCK clocks issued to shift in direction (rd/wr) bit and first 6 bits of Nexus reg. addr.
51SHIFT-DR EXIT1-DR (7th bit of Nexus reg. shifted in)
6 1 EXIT1-DR  UPDATE-DR (Nexus shifter is transferred to Nexus command register)
71UPDATE-DR SELECT-DR_SCAN
8 0 SELECT-DR_SCAN  CAPTURE-DR (Register value is transferred to Nexus shifter)
9 0 CAPTURE-DR  SHIFT-DR
10 0 (31) TCK clocks issued to transfer register value to TDO pin while shifting in TDI value
11 1 SHIFT-DR  EXIT1-DR (MSB of value is shifted in/out of shifter)
12 1 EXIT1-DR  UPDATE -DR (if access is write, shifter is transferred to register)
13 0 UPDATE-DR  RUN-TEST/IDLE (transfer complete - Nexus controller to reg. select state)