NXP Semiconductors PXN2020 - 8.3.2.11 External IRQ Digital Filter Register (SIU_IDFR)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-21
8.3.2.11 External IRQ Digital Filter Register (SIU_IDFR)
The SIU_IDFR specifies the amount of digital filtering on the IRQ0–IRQ15 pins. The digital filter length
field specifies the number of system clocks that define the period of the digital filter and the minimum time
a signal must be held in the active state on the IRQ pins to be recognized as an edge-triggered event.
Offset: SIU_BASE + 0x002C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
NFEE0
1
NFEE1
1
00000000000000
W
Reset0 0 00 000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IFEE
15
IFEE
14
IFEE
13
IFEE
12
IFEE
11
IFEE
10
IFEE
9
IFEE
8
IFEE
7
IFEE
6
IFEE
5
IFEE
4
IFEE
3
IFEE
2
IFEE
1
IFEE
0
W
Reset0 0 00 000000000000
1
Once written, the NFEEn bits cannot be changed until the next reset.
Figure 8-11. IRQ Falling-Edge Event Enable Register (SIU_IFEER)
Table 8-13. SIU_IFEER Field Descriptions
Field Function
NFEEn NMI Falling-Edge Event Enable n. These write-once bits enable rising-edge triggered events on the corresponding
NMIn input.
0 Falling edge event disabled.
1 Falling edge event enabled.
Note: Once written, the NFEEn bits cannot be changed until the next reset.
IFEEn IRQ Falling-Edge Event Enable n. Enables falling-edge triggered events on the corresponding IRQn pin.
0 Falling edge event disabled.
1 Falling edge event enabled.
Offset: SIU_BASE + 0x0030 Access: User read/write
0 1 2 3 4 5 6 7 8 9 101112131415
R0 0 00000000000000
W
Reset0 0 000 00000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0000000000
DFL
W
Reset0 0 000 00000000000
Figure 8-12. External IRQ Digital Filter Register (SIU_IDFR)