NXP Semiconductors PXN2020 - 29.3.4.7 Interrupt Masks 2 Register (CANx_IMASK2)

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-23
29.3.4.7 Interrupt Masks 2 Register (CANx_IMASK2)
This register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding CANx_IFLAG2 bit
is set).
IDLE CAN Bus IDLE State. This status bit indicates when CAN bus is in IDLE state.
0 No such occurrence.
1 CAN bus is now IDLE.
TXRX Current FlexCAN Status (Transmitting/Receiving). This status bit indicates if FlexCAN is transmitting or
receiving a message when the CAN bus is not in IDLE state. This bit has no meaning when IDLE is asserted.
0 FlexCAN is receiving a message (IDLE = 0).
1 FlexCAN is transmitting a message (IDLE = 0).
FLT_CONF Fault Confinement State. This status bit indicates the confinement state of the FlexCAN module. If the LOM bit
in the CANx_CTRL is asserted, the FLT_CONF field indicates “Error Passive”. Since the CANx_CTRL is not
affected by soft reset, the FLT_
CONF field is not affected by soft reset if the LOM bit is asserted.
00 Error active.
01 Error passive.
1n Bus off.
BOFF_INT Bus Off Interrupt. This status bit is set when FlexCAN is in the bus off state. If CANx_CTRL[BOFF_MSK] is set,
an interrupt is generated to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
0 No such occurrence.
1 FlexCAN module is in “Bus Off” state.
ERR_INT Error Interrupt. This status bit indicates that at least one of the error bits (bits 16–21) is set. If
CANx_CTRL[ERR_MSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
Writing 0 has no effect.
0 No such occurrence.
1 Indicates setting of any error bit in the CANx_ESR.
Offset: Base + 0x0024 Access: User read/write
0123456789101112131415
R
BUF
63M
BUF
62M
BUF
61M
BUF
60M
BUF
59M
BUF
58M
BUF
57M
BUF
56M
BUF
55M
BUF
54M
BUF
53M
BUF
52M
BUF
51M
BUF
50M
BUF
49M
BUF
48M
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
47M
BUF
46M
BUF
45M
BUF
44M
BUF
43M
BUF
42M
BUF
41M
BUF
40M
BUF
39M
BUF
38M
BUF
37M
BUF
36M
BUF
35M
BUF
34M
BUF
33M
BUF
32M
W
Reset0000000000000000
Figure 29-11. Interrupt Masks 2 Register (CANx_IMASK2)
Table 29-11. CANx_ESR Field Descriptions (continued)
Field Description