Resets
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 4-3
4.3.2.2 Low-Voltage Inhibit (LVI) Resets
The internal LVI reset signals are asserted when the voltage on the corresponding supply is below defined
values. The following are the LVI resets:
• LVI12—LVI on internal 1.2 V supply (V
DD
)
• LVI33—LVI on internal 3.3 V supply to I/O pads and flash (V
DD33
)
• LVISYN—LVI on 3.3 V V
DDSYN
supply
• LVIL_VDDA—LVI on V
DDA
input supply and generates reset
• LVI_VDDA—LVI on V
DDA
input supply and generates either a reset or an interrupt
— Reset: configured in the CRP_SOCSC register, reported in SIU_RSR register (default)
— Interrupt: configured and reported in CRP_SOCSC register
On assertion, the SIU_RSR[PORS] flag is set.
4.3.2.3 External Reset
When the reset controller detects assertion of the RESET pin, the internal reset signal is asserted. The
SIU_RSR[ERS] bit is set, and all other reset status bits in the SIU_RSR are cleared.
4.3.2.4 Loss-of-Lock Reset
A loss-of-lock reset occurs when the PLL loses lock and the loss-of-lock reset enable (LOLRE) bit in the
PLL enhanced synthesizer control register 2 (ESYNCR2) is set. The internal reset signal and RESET pin
are asserted. The SIU_RSR[LLRS] bit is set, and all other reset status bits in the SIU_RSR are cleared.
4.3.2.5 Loss-of-Clock Reset
A loss-of-clock reset occurs when a failure is detected in either the reference clock signal or PLL output
when the PLL is enabled. The internal reset signal and RESET pin are asserted. The SIU_RSR[LCRS] bit
is set, and all other reset status bits in the SIU_RSR are cleared.
4.3.2.6 Watchdog Timer Reset
A watchdog timer reset occurs when the SWT watchdog timer is enabled and a timeout occurs. The
internal reset signal and RESET pin are asserted. The SIU_RSR[WTRS] bit is set, and all other reset status
bits in the SIU_RSR are cleared.
4.3.2.7 Z6 Core Checkstop Reset
When the Z6 core enters a checkstop state, and the checkstop reset is enabled (SIU_SRCR[CRE0] bit), a
checkstop reset occurs. The internal reset signal and RESET
pin are asserted. The SIU_RSR[CRS] bit is
set and all other reset status bits in the SIU_RSR are cleared.
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