Semaphores
PXN20 Microcontroller Reference Manual, Rev. 1
15-4 Freescale Semiconductor
15.3.2 Register Descriptions
This section lists the semaphores registers in address order and describes the registers and their bit fields.
15.3.2.1 Semaphores Gate n Register (SEMA4_GATEn)
Each semaphore gate is implemented in a 2-bit finite state machine, right-justified in a byte data structure.
The hardware uses the bus master number in conjunction with the data patterns to validate all attempted
write operations. Only processor bus masters can modify the gate registers. After it is locked, a gate must
be opened (unlocked) by the locking processor core.
0x0007 SEMA4_Gate07—Semaphores gate 7 R/W 0x00 15.3.2.1/15-4
0x0008 SEMA4_Gate08—Semaphores gate 8 R/W 0x00 15.3.2.1/15-4
0x0009 SEMA4_Gate09—Semaphores gate 9 R/W 0x00 15.3.2.1/15-4
0x000A SEMA4_Gate10—Semaphores gate 10 R/W 0x00 15.3.2.1/15-4
0x000B SEMA4_Gate11—Semaphores gate 11 R/W 0x00 15.3.2.1/15-4
0x000C SEMA4_Gate12—Semaphores gate 12 R/W 0x00 15.3.2.1/15-4
0x000D SEMA4_Gate13—Semaphores gate 13 R/W 0x00 15.3.2.1/15-4
0x000E SEMA4_Gate14—Semaphores gate 14 R/W 0x00 15.3.2.1/15-4
0x000F SEMA4_Gate15—Semaphores gate 15 R/W 0x00 15.3.2.1/15-4
0x0010–0x003F Reserved
00x040 SEMA4_CP0INE—Semaphores CP0 IRQ notification enable R/W 0x0000 15.3.2.2/15-5
0x0042–0x0047 Reserved
0x0048 SEMA4_CP1INE—Semaphores CP1 IRQ notification enable R/W 0x0000 15.3.2.2/15-5
0x004A–0x07F Reserved
0x0080 SEMA4_CP0NTF—Semaphores CP0 IRQ notification R 0x0000 15.3.2.3/15-6
0x008 2–00x087 Reserved
0x0088 SEMA4_CP1NTF—Semaphores CP1 IRQ notification R 0x0000 15.3.2.2/15-5
0x008A–0x00FF Reserved
0x0100 SEMA4_RSTGT—Semaphores reset gate R/W 0x0000 15.3.2.4/15-6
0x0102 Reserved
0x0104 SEMA4_RSTNTF—Semaphores reset IRQ notification R/W 0x00000 15.3.2.5/15-8
0x0106–0x3FFF Reserved
Table 15-1. Semaphores Memory Map (continued)
Offset from
SEMA4_BASE
(0xFFF1_0000)
Register Access Reset Value
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