NXP Semiconductors PXN2020 - 28.3.2.1 eMIOS200 Module Configuration Register (EMIOS_MCR)

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-9
28.3.2.1 eMIOS200 Module Configuration Register (EMIOS_MCR)
The EMIOS_MCR contains global control bits for the eMIOS200 block.
Offset: EMIOS_BASE + 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MDIS FRZ GTBE
0
GPREN
0000000000
W
Reset00000 0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GPRE[0:7]
00000000
W
Reset00000 0 0000000000
Figure 28-3. eMIOS200 Module Configuration Register (EMIOS_MCR)
Table 28-5. EMIOS_MCR Field Descriptions
Field Description
bit 0 Reserved.
Note: Writing to this bit updates the register value, and reading it returns the last value written, but the bit has
no other effect.
MDIS Module Disable Bit. Puts the eMIOS200 in low-power mode. The MDIS bit is used to stop the clock of the
block, except the access to registers EMIOS_MCR, EMIOS_OUDR, and EMIOS_UCDIS.
0 Clock is running.
1 Enter low-power mode.
FRZ Freeze Bit. Enables the eMIOS200 to freeze the registers of the unified channels when debug mode is
requested at MCU level. Each unified channel must have FREN bit set in order to enter freeze mode. While
in freeze mode, the eMIOS200 continues to operate to allow the MCU access to the unified channel registers.
The unified channel remains frozen until the FRZ bit is written to 0 or the MCU exits debug mode or the unified
channel FREN bit is cleared.
0 Exit freeze mode.
1 Stops unified channel operation when in debug mode and the FREN bit is set in the EMIOS_CCR[n]
register.
GTBE Global Time Base Enable Bit. The GTBE bit is used to export a global time base enable from the module and
provide a method to start time bases of several blocks simultaneously.
0 Global time base enable out signal negated.
1 Global time base enable out signal asserted.
Note: The global time base enable input pin controls the internal counters. When asserted, internal counters
are enabled. When negated, internal counters are disabled.