FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-50 Freescale Semiconductor
The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control
Register (TICCR). For a detailed description of timer T2, refer to Section 26.6.17.2, Absolute / Relative
Timer T2.
NOTE
If timer T2 is configured as an absolute timer and the application modifies
the values in this register while the timer is running, the change becomes
effective immediately and the timer T2 will expire according to the changed
values.
If timer T2 is configured as a relative timer and the application changes the
values in this register while the timer is running, the change becomes
effective when the timer has expired according to the old values.
26.5.2.44 Slot Status Selection Register (SSSR)
This register is used to access the four internal non memory-mapped slot status selection registers SSSR0
to SSSR3. Each internal registers selects a slot, or symbol window/NIT, whose status vector will be saved
in the corresponding Slot Status Registers (SSR0–SSR7) according to Table 26-52. For a detailed
description of slot status monitoring, refer to Section 26.6.18, Slot Status Monitoring.
Table 26-50. TI2CR1 Field Descriptions
Field Description
Fields for absolute timer T2 (TICCR[T2_CFG] = 0)
T2_MTOFFSET Timer T2 Macrotick Offset — This field holds the macrotick offset value for timer T2.
Fields for relative timer T2 (TICCR[T2_CFG] = 1)
T2_MTCNT[15:0] Timer T2 Macrotick Low Word — This field defines the low word of the macrotick value for timer T2.
Base + 0x0064 16-bit write access required Write: Anytime
0123456789101112131415
R0 0
SEL
0
SLOTNUMBER
WWMD
Reset0000000000000000
Figure 26-44. Slot Status Selection Register (SSSR)
Table 26-51. SSSR Field Descriptions
Field Description
WMD Write Mode — This control bit defines the write mode of this register.
0 Write to all fields in this register on write access.
1 Write to SEL field only on write access.
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